Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning

Abstract

The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality and output quality. In this paper, we introduce a significance-aware code vulnerability factor (SCVF) for early evaluation of the impact of such errors on applications. To estimate this metric, we propose the utilization of a microarchitecture-aware ML model for timing error prediction that jointly considers many instruction types, as well as all in-flight instructions in a pipeline. Finally, we validate the efficacy of SCVF by analyzing the output quality loss of various applications.

Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations

“…• We develop workload-aware error prediction models based on supervised ML techniques under various, critical operating regions, unlike [14]. To achieve this, we developed a unique framework, that allowed us to extract relevant features from pipelined cores under different operating settings.…”

“…Such a work revealed that instruction execution history needs to be incorporated into timing error modelling, yet it did not consider it as a feature during ML model training for bit-level timing error prediction. Although a more recent study [14] incorporated instruction execution history in MLbased timing error modelling, the results are constrained to a single set of operating settings and there are not any suggested techniques (e.g., precision scaling) to improve the speed of the developed models as we do.…”

“…d) Training process: We utilize Random Forest (RF), a widely used supervised classification algorithm, using the scikit-learn framework of python, which is consistent with what have been reported in prior ML-based prediction studies [11], [14], [15]. We utilize a tuning technique (i.e., grid search) to fine-tune the hyperparameters of our model, to achieve better results.…”

“…In fact, most timing error models assume a fixed probability that is unaware of workload (i.e., instruction type and its input operands) and microarchitecture properties [8], which may simplify modelling but leads to inaccurate estimations. Existing studies have tried to capture the workload-dependent parameters by developing timing error models using complex statistical methods based on expensive gate-level simulations (GLS) and most recently based on ML methods [9]- [14]. Such studies may have showcased the potential of using ML on error prediction, but have left a lot of room for improvement.…”

“…Such studies may have showcased the potential of using ML on error prediction, but have left a lot of room for improvement. Actually, recent studies have either neglected important microarchitecture features [11], [12], [15] or have left unexplored more critical operating regions [14]. Moreover, they have not yet exploited approximate computing techniques, that could enable trade-offs between accuracy and inference time (required prediction time per sample), which may prove useful in speeding up error injection campaigns and realizing effective run-time error-aware system power management schemes.…”