Estimation of High Performance 3T DRAM Cell at Nanometer Technology

Abstract

In this paper the analysis of conventional DRAM logic compatible 3T gain cell has been shown. In this paper 3T dram with semantic design technique is presented. The read and write operation for single bit storage is useful in terms of leakage power, static power dissipation, signal to noise ratio and delay time. The simulation result shows that when a wide range of operating voltage is taken, which is from 0.7 to 1.3 V then it is observed that low voltage operation is suitable for low read access time but the leakage power dissipation increases as increase in the range of operating voltage. The design has been carried out at the 45 nm scale technology on cadence virtuoso simulating tool.