Estimation of Mathematical Function by Stochastic Logic

Abstract

Recent application demand high speed and robustness with small area and low power consumptions. Much pupation in nanometer scale technology in VLSI dimension of transistors goes on reducing. On the other hand increasing number of transistors leads to leakage current so Circuit becomes unreliable. Additionally, if transistors are replacing by other devices it does not yield satisfied result. Owning to these complications an alternative method for computing technique called stochastic logic. This paper described a stochastic implementation for various mathematical functions which analyses the area, power consumption, delay, efficiency. Logic implementations overcome the disadvantages of conventional methods.