Ethernet controller SoC design and its low-power DFT considerations

Abstract

In this paper, an Ethernet controller SoC solution and its low power design for testability (DFT) for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit (MCU), media access control (MAC) circuit and embedded memories such as static random access memory (SRAM), read only memory (ROM) and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits: the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test (BIST). By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor (CMOS) technology, the die area is 4.8×4.6 mm 2 . Test results show that the maximum throughput of Ethernet packets may reach 7 Mb s 1 .

Capacity Prediction of VRLA Batteries Based on Stepwise Regression Analysis

“…They are only discharged or charged under equalizing conditions when there is an AC power loss in substations [7]. [8], [9], and [10] mention that factors such as temperature, charge and discharge cycle count, single charging duration, and cumulative charging duration can affect the capacity variation of VRLA batteries. Experimental data are collected using the battery discharge system, including cycle count, duration, capacity, voltage range, and temperature.…”