EUV photomask defects: what prints, what doesn't, and what is required for HVM

Rankin, Jed; Qi, Zhengqing John; Lawliss, Mark; Narita, Eisuke; Seki, Kazunori; Badger, Karen; Bonam, Ravi; Halle, Scott; Turley, Christina

doi:10.1117/12.2197476

Cited by 7 publications

(7 citation statements)

References 11 publications

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“…12,33,34 To identify all potential defects buried in the multilayer stack, actinic blank inspection (ABI) at 13.5 nm is required. 13 Despite the potential impact on the conclusions made in this work, actinic inspection tools under development are not considered as it is uncertain when ABI and actinic pattern mask inspection tools will reach HVM availability.…”

Section: Viability Of Defect-free Masks For 7 Nm Nodementioning

confidence: 99%

“…5 Recent efforts have limited blank defects greater than 54 nm in size, 6 however much experimental work have shown that smaller defects also requires elimination. [7][8][9][10][11][12][13] The lack in highvolume availability of pristine defect-free blanks as well as the absence of a robust mask repair technique 14,15 mandates defect mitigation through pattern shift for intersecting HVM. By using known defect locations on a blank, the mask design can be intentionally shifted to avoid patterning a desired reflective region directly over a defect.…”

Section: Introductionmentioning

confidence: 99%

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Defect avoidance for EUV photomask readiness at the 7 nm node

Rankin

Narita

et al. 2016

SPIE Proceedings

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Several challenges hinder extreme ultraviolet lithography (EUVL) photomask fabrication and its readiness for high volume manufacturing (HVM). The lack in availability of pristine defect-free blanks as well as the absence of a robust mask repair technique mandates defect mitigation through pattern shift for the production of defect-free photomasks. The work presented here provides a comprehensive look at pattern shift implementation to intersect EUV HVM for the 7 nm technology node. An empirical error budget to compensate for measurement variability and errors, based on the latest HVM inspection and write tool capabilities, is first established and then experimentally verified. The validated error budget is applied to 20 representative EUV blanks and pattern shift is performed on fully functional 7 nm node chip designs. The probability of defect-free masks is explored for various layers, including metal, contact, and gate cut layers. From these results, an assessment is made on the current viability of defect-free EUV masks and what is required to construct a complete defect-free EUV mask set.

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Section: Viability Of Defect-free Masks For 7 Nm Nodementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Defect avoidance for EUV photomask readiness at the 7 nm node

Rankin

Narita

et al. 2016

SPIE Proceedings

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“…This reflective design introduces a new class of defects not seen in previous mask technologies. [4][5][6][7][8][9] As such, EUV mask defectivity remains a persistent obstacle that must be addressed in order to enable EUVL high-volume manufacturing (HVM).…”

Section: Introductionmentioning

confidence: 99%

Evaluation of multilayer defect repair viability and protection techniques for extreme ultraviolet masks

Isogawa¹,

Seki²,

Lawliss

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

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“…10 An approximate signature of buried defects can also be captured by mask optical inspection in a phase contrast mode. This information can assist mask known defect locations to filter out process and mask use added defect data.…”

Section: Introductionmentioning

confidence: 99%

EUV mask and wafer defectivity: strategy and evaluation for full die defect inspection

et al. 2016

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Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM). 1, 2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable. 3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing.In this work, we assess mutltiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.

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EUV photomask defects: what prints, what doesn't, and what is required for HVM

Cited by 7 publications

References 11 publications

Defect avoidance for EUV photomask readiness at the 7 nm node

Defect avoidance for EUV photomask readiness at the 7 nm node

Evaluation of multilayer defect repair viability and protection techniques for extreme ultraviolet masks

EUV mask and wafer defectivity: strategy and evaluation for full die defect inspection

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