Evaluating Controlled Memory Request Injection to Counter PREM Memory Underutilization

Cavicchioli, Roberto; Capodieci, Nicola; Solieri, Marco; Bertogna, Marko; Valente, Paolo; Marongiu, Andrea

doi:10.1007/978-3-030-63171-0_5

Cited by 3 publications

(8 citation statements)

References 14 publications

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“…Controlled Memory-Request Injection (CMRI) [11] has been recently proposed as a conceptual model to improve DRAM bandwidth utilization for PREM workloads deployed on multi-core CPU. The problem of memory bandwidth underutilization is even more stringent in a modern HeSoC, where the DRAM bandwidth is designed to sustain requests from the accelerators and is is scarcely used by the CPU cores.…”

Section: Supporting Controlled Memory Request Injection In Hesocsmentioning

confidence: 99%

“…This article is mainly inspired by the conference paper where CMRI has been first proposed [11]. This work employs a much cleaner experimental setup (bare-metal applications on paritioning hypervisor instead of embedded Linux application).…”

Section: Related Workmentioning

confidence: 99%

“…Controlled Memory Request Injection (CMRI) [11] was recently discussed as a novel concept to enabling fine-grained control of the unused bandwidth in PREM-like schemes. CMRI promises better usage of DRAM bandwidth while at the same time maintaining the task under service's latency increase within acceptable bounds.…”

Section: Introductionmentioning

confidence: 99%

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Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs

Brilli

Cavicchioli

Solieri³

et al. 2022

ACM Trans. Embed. Comput. Syst.

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High-performance embedded platforms are increasingly adopting heterogeneous systems-on-chip (HeSoC) that couple multi-core CPUs with accelerators such as GPU, FPGA or AI engines. Adopting HeSoCs in the context of real-time workloads is not immediately possible, though, as contention on shared resources like the memory hierarchy – and in particular the main memory (DRAM) – causes unpredictable latency increase. To tackle this problem, both the research community and certification authorities mandate (i) that accesses from parallel threads to the shared system resources (typically, main memory) happen in a mutually exclusive manner by design, or (ii) that per-thread bandwidth regulation is enforced. Such arbitration schemes provide timing guarantees, but make poor use of the memory bandwidth available in a modern HeSoC. Controlled Memory Request Injection (CMRI) is a recently-proposed bandwidth limitation concept that builds on top of a mutually-exclusive schedule but still allows the threads currently not entitled to access memory to use as much of the unused bandwidth as possible without losing the timing guarantee. CMRI has been discussed in the context of a multi-core CPU, but the same principle applies also to a more complex system such as an HeSoC. In this paper we introduce two CMRI schemes suitable for HeSoCs: Voluntary Throttling via code refactoring and Bandwidth Regulation via dynamic throttling. We extensively characterize a proof-of-concept incarnation of both schemes on two HeSoCs: an NVIDIA Tegra TX2 and a Xilinx UltraScale+, highlighting the benefits and the costs of CMRI for synthetic workloads that model worst-case DRAM access. We also test the effectiveness of CMRI with real benchmarks, studying the effect of interference among the host CPU and the accelerators.

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Section: Supporting Controlled Memory Request Injection In Hesocsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs

Brilli

Cavicchioli

Solieri³

et al. 2022

ACM Trans. Embed. Comput. Syst.

Self Cite

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“…Although effective at guaranteeing predictable timing of memory accesses, PREM and PREM-like approaches [7], [8] greatly under-utilize memory bandwidth, which in HeSoCs is designed to concurrently serve multiple computing units. Recently, Controlled Memory Request Injection (CMRI) has been proposed as a technique that can operate on top of PREM-like schemes, enabling fine-grained control of the unexploited bandwidth [9].…”

Section: Introductionmentioning

confidence: 99%

“…Most papers studying this problem target multi-core CPUs [1], [10] or GPU-based HeSoCs [2], [6], [11], while not much has been done so far in the context of FPGAbased HeSoCs. This paper aims at filling this gap by means of: i) extensive memory interference characterization on two state-of-the-art FPGA-based HeSoCs for high-end embedded systems: the Xilinx Zynq UltraScale+ ZU9EG and the Xilinx Versal VC1902 ACAP; ii) an implementation of the CMRI technique [9] suitable for generic FPGA accelerators; iii) a thorough assessment of the resulting benefits on the memory bandwidth exploitation.…”

Section: Introductionmentioning

confidence: 99%

Understanding and Mitigating Memory Interference in FPGA-based HeSoCs

Brilli

Capotondi

Burgio

et al. 2022

2022 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Like most high-end embedded systems, FPGA-based systems-on-chip (SoC) are increasingly adopting heterogeneous designs, where CPU cores, the configurable logic and other ICs all share interconnect and main memory (DRAM) controller. This paradigm is scalable and reduces production costs and time-tomarket, but creates resource contention issues, which ultimately affects the programs' timing. This problem has been widely studied on CPU-and GPU-based systems, along with strategies to mitigate such effects, but little has been done so far to systematically study the problem on FPGA-based SoCs. This work provides an in-depth analysis of memory interference on such systems, targeting two state-of-the-art commercial FPGA SoCs. We also discuss architectural support for Controlled Memory Request Injection (CMRI), a technique that has proven effective at reducing the bandwidth under-utilization implied by naive schemes that solve the interference problem by only allowing mutually exclusive access to the shared resources. Our experimental results show that: i) memory interference can slow down CPU tasks by up to 16× in the tested FPGA-based SoCs; ii) CMRI allows to exploit more than 40% of the memory bandwidth available to FPGA accelerators (normally completely unused in PREM-like schemes), keeping the slowdown due to interference below 10%.

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Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs

Brilli,

Valente,

Capotondi

et al. 2023

2023 60th ACM/IEEE Design Automation Conference (DAC)

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Evaluating Controlled Memory Request Injection to Counter PREM Memory Underutilization

Cited by 3 publications

References 14 publications

Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs

Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs

Understanding and Mitigating Memory Interference in FPGA-based HeSoCs

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs

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