Evaluating Latency in Multiprocessing Embedded Systems for the Smart Grid

Self Cite

Modern multiprocessing embedded applications require, in many cases, two different environments on the same platform: one that meets real-time requirements and another one with a general purpose operating system. Although several technologies can be used, two of the most popular are virtualization based on hypervisors and asymmetric multiprocessing software. However, using these tools introduces latency, which must be measured to verify compliance with real-time requirements. With the aim of facilitating these measurements, this work provides a hardware tool that is more precise and easier to use than other existing software solutions. The paper also studies the interrupt latency generated by different hypervisors and asymmetric multiprocessing frameworks in a Zynq UltraScale+ platform. This research work facilitates the accurate study of the temporal response of multiprocessor embedded systems, which allows for evaluating their suitability for applications with real-time requirements.

Section: Related Workmentioning

confidence: 99%

Interrupt Latency Accurate Measurement in Multiprocessing Embedded Systems by Means of a Dedicated Circuit

Alonso,

Muguira,

Garate

et al. 2024

Self Cite

“…In a real-time Linux environment, we employed the cyclictest benchmarking tool to evaluate the scheduling latency of each ISA. Cyclictest measures the difference between a thread's intended wake-up time and the time it wakes up for each ISA [44]. A previous study [30] used cyclictest on a Preempt-RT patched Linux system to assess the real-time performance of RISC-V.…”

Section: Scheduling Latencymentioning

confidence: 99%

Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System

Yoo,

Choi

2024

RISC-V offers a modular technical approach combined with an open, royalty-free instruction set architecture (ISA). However, despite its advantages as a fundamental building block for many embedded systems, the escalating complexity and functional demands of real-time applications have made adhering to response time deadlines challenging. For real-time applications of RISC-V, real-time performance analysis is required for various ISAs. In this paper, we analyze the real-time performance of RISC-V through two real-time approaches based on processor architectures. For real-time operating system (RTOS) applications, we adopted FreeRTOS and evaluated its performance on HiFive1 Rev B (RISC-V) and STM3240G-EVAL (ARM M). For real-time Linux, we utilized Linux with the Preempt-RT patch and tested its performance on VisionFive 2 (RISC-V), MIO5272 (x86-64), and Raspberry Pi 4 B (ARM A). Through these experiments, we examined the response times on the real-time mechanisms of each operating system. Additionally, in the Preempt-RT experiments, scheduling latencies were evaluated by means of the cyclictest. These are very important parameters for implementing real-time applications comprised of multi-tasking. Finally, in order to show the real-time capabilities of RISC-V practically, we implemented motion control of a six-axis collaborative robot, which was performed on the VisionFive 2. This implementation provided a comparative result of RISC-V’s performance against the x86-64 architecture. Ultimately, the results indicated that the real-time performance of RISC-V for real-time applications was feasible. A noticeable achievement of this research is its first implementation of an EtherCAT master on RISC-V designed for real-time applications. The successful implementation of the EtherCAT master on RISC-V shows real-time capabilities for a wide range of real-time applications.

“…The latencies of the timer interrupts are measured in [20] for four scenarios, namely standalone, FreeRTOS, Linux + standalone, and Linux+FreeRTOS. Linux thread latencies are evaluated in [21] for smart grid end-point applications where 3 ms is the limit. Eight scenarios are considered, with two of them applying the open-source Xen hypervisor (hypervisor is an additional software layer that enables having different OSs in a homogeneous platform).…”

Section: Related Workmentioning

confidence: 99%

Dual-Core PLC for Cooperating Projects with Software Implementation

Hubacz,

Trybus

2023

Development of a general-purpose PLC based on a typical dual-core processor as a hardware platform is presented. The cores run two cooperating projects involving data exchange through shared memory. Such a solution is equivalent to a single-core PLC running two tasks by means of a real-time operating system. Upgrading to a typical programming tool involves defining which of the global variables are shared, and whether a variable in a particular core is read-from or written-to the shared memory. Extensions to core runtimes consist of read-from at the beginning of the scan cycle and write-to at the end, and of an algorithm for protecting the shared memory against access conflicts. As an example, the proposed solution is implemented in an engineering tool with runtime based on a virtual machine concept. The PLC prototype is based on a heterogeneous ARM dual-core STM32 microcontroller running different projects. The innovation in the research lies in showing how to run two projects in a dual-core PLC without using an operating system. Extension to multiple projects for a multi-core processor is can be accomplished in a similar manner.