Evaluating Possibilities for Formally Sound Simulation and Verification of VHDL

Abstract

Formal verification is a promising way to ensure correctness of digital cuircuits. VHDL is an important standard in descripting digital circuits. This paper gives a survey about the state of the art in bringing formal verification and VHDL together. Up to now, there is no unique and best solution for the formal verification of arbitrary descriptions. The survey notes serveral aspects, which has been traded off against each other: "degree of automation", "supported VHDL subset", "practical usability", "confidence of the approach", to name just some. The existing approaches are compared with redard to these aspects. The reader gets an overview of the possibilities and limitations of different approaches with regard to simulation, symbolic simulation and formal verification. Finally, the formal VHDL environment created by the authors is presented.