Evaluating the impact of simultaneous multithreading on network servers using real hardware

Abstract

This paper examines the performance of simultaneous multithreading (SMT) for network servers using actual hardware, multiple network server applications, and several workloads. Using three versions of the Intel Xeon processor with Hyper-Threading, we perform macroscopic analysis as well as microarchitectural measurements to understand the origins of the performance bottlenecks for SMT processors in these environments. The results of our evaluation suggest that the current SMT support in the Xeon is application and workload sensitive, and may not yield significant benefits for network servers.In general, we find that enabling SMT on real hardware usually produces only slight performance gains, and can sometimes lead to performance loss. In the uniprocessor case, previous studies appear to have neglected the OS overhead in switching from a uniprocessor kernel to an SMT-enabled kernel. The performance loss associated with such support is comparable to the gains provided by SMT. In the 2-way multiprocessor case, the higher number of memory references from SMT often causes the memory system to become the bottleneck, offsetting any processor utilization gains. This effect is compounded by the growing gap between processor speeds and memory latency. In trying to understand the large gains shown by simulation studies, we find that while the general trends for microarchitectural behavior agree with real hardware, differences in sizing assumptions and performance models yield much more optimistic benefits for SMT than we observe.

Analyzing the Effects of Hyperthreading on the Performance of Data Management Systems

“…We can see that we exhibit a detrimental effect at the L1 data cache level. This result is similar to those seen on network servers on the Xeon processor [19]. The increase in the L1 data cache load miss rate ranges from 3.5% to 5.4% (excluding the single thread case).…”

“…Both beneficial and detrimental patterns have been reported on the Intel Pentium 4 hyper-threaded processor L1 and L2 caches for Java Applications [16]. Beneficial patterns for L2 cache and detrimental patterns for L1 cache in network servers [19] have been reported on the Intel Xeon hyper-threaded processor. Figure 4a gives the L1 data cache miss rate for load instructions.…”

“…The impact of SMT on network servers using the Intel Xeon processor [19] shows that enabling SMT produces only slight performance gains and can sometimes lead to performance loss. A characterization of SMT in the IBM Power 5 machine [20] shows that the biggest single factor affecting SMT gain is the effect of load and store activities.…”

A Superscalar software architecture model for Multi-Core Processors (MCPs)

“…Instead of designing a software scheme to implement any server architecture, most prior studies (Welsh et al, 2001;Choi et al, 2005;Ruan et al, 2005) have mainly proposed and conducted performance evaluation of Web server architectures on SMP/SoC machines. Welsh et al (2001) proposed the new Web server architecture, called State Event-Driven Architecture (SEDA), combining the ED and MT models, and conducted performance comparison through real implementation on a small SMP machine.…”

“…They conducted performance comparison among several Web server architectures through simulation and showed that their proposed model can outperform other models across various system and workload parameters. Next, Ruan et al (2005) evaluated the impact of Simultaneous Multithreading (SMT) on various Web servers with three versions of the Intel Xeon processor and showed that SMT has limitations to yield significant performance improvement. Their evaluation was conducted on 2 CPUs and 4 SMTs.…”