Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

Livramento, Vinicius; Guth, Chrystian; Güntzel, José Luís; Johann, Marcelo

doi:10.1109/lascas.2012.6180359

Cited by 2 publications

(4 citation statements)

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“…Particularly, Coudert [1997] pointed out that the impact on the second level of fanins (gates G 3 and G 5 ) and fanouts (registers R 1 and R 2 ) is too time consuming and has an impact of ≈ 1% on delay. In our previous work [Livramento et al 2012] we have also evaluated the impact of considering only one level of fanin and fanout using a sensitivity-based heuristic on ISCAS85 benchmarks, and we concluded that considering only the immediate fanins and fanouts can reduce the runtime by ≈44%. We also experimented our LR-based technique on circuits DMA slow and pci bridge32 slow and found out that accounting for one level of fanin and fanout is twice as fast as accounting for two levels.…”

Section: Algorithm 2: Solve Lrs2mentioning

confidence: 95%

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Livramento

Guth

Güntzel

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discrete nature of the problem, along with complex timing models, stringent design constraints, and ever-increasing circuit sizes, make the problem very difficult to tackle. Lagrangian Relaxation (LR) is an effective technique to handle complex constrained optimization problems and therefore has been successfully applied to solve the gate sizing problem. This article proposes an improved Lagrangian relaxation formulation for discrete gate sizing that relaxes timing, maximum gate input slew, and maximum gate output capacitance constraints. Based on such formulation, we propose a hybrid technique composed of three steps. First, a topological greedy heuristic solves the LR formulation. Such a heuristic is applied assuming a slightly increased target clock period (backoff factor) to better explore the solution space. Second, a delay recovery heuristic reestablishes the original target clock with small power overhead. Third, a power recovery heuristic explores the remaining slacks to further reduce power. Experiments on the ISPD 2012 Contest benchmarks show that our hybrid technique provides less leakage power than the state-of-the-art work for every circuit from the ISPD 2012 Contest infrastructure, achieving up to 24% less leakage. In addition, our technique achieves a much better compromise between leakage reduction and runtime, obtaining, on average, 9% less leakage power while running 8.8 times faster. ACM Reference Format: Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, and Marcelo O. Johann. 2014. A hybrid technique for discrete gate sizing based on lagrangian relaxation.

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Section: Algorithm 2: Solve Lrs2mentioning

confidence: 95%

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Livramento

Guth

Güntzel

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

Self Cite

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“…Gate sizing is very useful in reducing power [7,8]. It consists of substituting the big cells that are in the non-timing critical path by smaller gates that satisfy the delay requirement with identical logical function.…”

Section: The Basic Concept Of Power Calculation and Optimizationmentioning

confidence: 99%

“…Most of the published research on power reduction techniques at the circuit level adopt a bottom-up methodology and treat the power issue on a gate level [7][8][9], which means that they prove the effectiveness of a technique on a design with few gates and then try to generalize on multi-million gates designs. In some cases, if we apply such a technique on a gate, the power and timing of neighboring gates may be impacted, as presented in [8].…”

Section: Max Transition Variation Impact On Power Optimization (Case mentioning

confidence: 99%

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Evaluating the Impact of Max Transition Constraint Variations on Power Reduction Capabilities in Cell-Based Designs

Chentouf¹,

Ismaili

2017

JLPEA

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Abstract:Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools to meet the power requirement. In this paper, we will evaluate, independently from the library file, the impact of redefining the max transition constraint (MTC) before the power optimization phase, and we will study the impact of over-constraining or under-constraining a design on power in order to find the best trade-off between design constraining and power optimization. Experimental results showed that power optimization depends on the applied MTC and that the MTC value corresponding to the best power reduction results is different from the default MTC. By using a new MTC definition method on several designs, we found that the power gain between the default methodology and the new one reaches 2.34%.

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Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

Cited by 2 publications

References 15 publications

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Evaluating the Impact of Max Transition Constraint Variations on Power Reduction Capabilities in Cell-Based Designs

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