Evaluating the Optimized Implementations of SNOW3G and ZUC on FPGA

Zhang, Lingchen; Xia, Luning; Liu, Zongbin; Jing, Jiwu; Ma, Yuan

doi:10.1109/trustcom.2012.150

Cited by 21 publications

(19 citation statements)

References 3 publications

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“…On FPGA platform, the new architecture increases the throughput by 45%, compared with the latest work [10], and saves nearly 12% of hardware resource. On ASIC platform, our new architecture provides at least twice the throughput compared to any existing academic designs and commercial designs.…”

Section: Contributionmentioning

confidence: 99%

“…Without using pipeline architecture, Wang et la [8] and Zhang et al [10] proposed architectures based on carry save adder (CSA) for implementing the ZUC algorithm on FPGA, they still cannot overcome the obstacle that the path in the initialization stage is longer than that in the working stage, despite involving carry save adder to shorten the critical path.…”

Section: The State-of-the-art Implementation Of Zuc In Hardwarementioning

confidence: 99%

“…(Carry 3 , Sum In the Pipeline Stage 2, the CSA component is used to calculate (Carry 3 , Sum 3 ) using equation (10). At the end of this stage, the modulo 2 31 − 1 adder with Method 2 is used to derive S 16 which is the value of S 15 in the next iteration.…”

Section: The Mixed Two-stage Pipeline Architecture Of Zucmentioning

confidence: 99%

“…If this checking step was included in this stage, it would extend the path in the Pipeline Stage 2. However, Zhang et al [10] has proofed this step can be ignored in the hardware implementation of ZUC.…”

Section: The Mixed Two-stage Pipeline Architecture Of Zucmentioning

confidence: 99%

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HPAZ: a High-throughput Pipeline Architecture of ZUC in Hardware

Liu

Zhang

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract. In this paper, we propose a high-throughput pipeline architecture of the stream cipher ZUC which has been included in the security portfolio of 3GPP LTE-Advanced. In the literature, the schema with the highest throughput only implements the working stage of ZUC. The schemas which implement ZUC completely can only achieve a much lower throughput, since a self-feedback loop in the critical path significantly reduces operating frequency. In this paper we design a mixed two-stage pipeline architecture which not only completely implements ZUC but also significantly raises the throughput. We have implemented our architecture on FPGA and ASIC. On FPGA platform, the new architecture increases the throughput by 45%, compared with the latest work, and particularly the new architecture also saves nearly 12% of hardware resource. On 65nm ASIC technology, the throughput of the new design can up to 80Gbps, which is 2.7 times faster than the fastest one in the literature, in particularly, it also saves at least 40% of hardware resource. In addition to the academic design, compared with the fastest commercial design, the new architecture doubles the throughput of that. To the best of our knowledge, this evaluation result is so far the best outcome. It can be assumed that hardware implementations of ZUC following our architecture will fit in future LTE equipments better.

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Section: Contributionmentioning

confidence: 99%

Section: The State-of-the-art Implementation Of Zuc In Hardwarementioning

confidence: 99%

Section: The Mixed Two-stage Pipeline Architecture Of Zucmentioning

confidence: 99%

Section: The Mixed Two-stage Pipeline Architecture Of Zucmentioning

confidence: 99%

See 2 more Smart Citations

HPAZ: a High-throughput Pipeline Architecture of ZUC in Hardware

Liu

Zhang

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

Self Cite

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“…LTE is a candidate for a project of 3GPP (3rd Generation Partnership Project).The growing demands on mobile services have encouraged many researchers toward achieving multi-services with low latency. To illustrate that, Lingchen Zhang in 2012 [10] pointed out the LTE (Long Term Evolution) is a standard for high-speed wireless data communications which is maintained as a project of the 3rd Generation Partnership Project (3GPP). In addition, to cover the requirements of the mobile migrations of Internet applications, such as VOIP, video streaming, music downloading and mobile TV, LTE networks offer the capacity to tolerate the throughput explosion for the connection from mobile devices customized to those new mobile applications.…”

Section: Introductionmentioning

confidence: 99%

Overview of ZUC Algorithm and its Contributions on the Security Success and Vulnerabilities of 4G Mobile Communication

Sulaiman¹

2017

IJCA

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With tremendous challenges in mobile communication toward a very advanced security level against new threats, ZUC algorithm emerged to overpass various algorithms that common before. ZUC is a stream cipher which is the core of the both newly LTE algorithms (LTE encryption and integrity algorithms). Nowadays, a mobile has been a crucial thing in people's daily life and people used to save their information including personal information on it. In addition, the accelerated change in mobile generations requires an appropriate algorithm to cope with the change and achieve more security demands. Therefore, Chinese cryptography experts have been designed ZUC algorithm to cope with 4G mobile security to overcome the obstacles that the previous generation had before with a flexibility to develop and change. The purpose of this research is to provide an extensive study on the ZUC algorithm and show the improvements that have been done till now and the vulnerabilities of the ZUC algorithm against different attacks.

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