Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs

Ishihara, Shingo; Xia, Zhengfan; Hariyama, Masanori; Kameyama, Michitaka

doi:10.5573/jsts.2010.10.3.165

Cited by 5 publications

(1 citation statement)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Papers such as [2] explored the applications of asynchronous technology. Because asynchronous design has the ability to interface with varied environments operating at different rates, they are useful for the design of System on Chip (SoC) [3], and also suitable for low power design method such as adaptive voltage scaling [4], [5]. Many asynchronous products and experimental chips have also been announced.…”

Section: Introductionmentioning

confidence: 99%

Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates

Xia

Ishihara

Hariyama

et al. 2012

IEICE Trans. Electron.

Self Cite

View full text Add to dashboard Cite

This paper introduces a novel design method of an asynchronous pipeline based on dual-rail dynamic logic. The overhead of handshake control logic is greatly reduced by constructing a reliable critical datapath, which offers the pipeline high throughput as well as low power consumption. Synchronizing Logic Gates (SLGs), which have no data dependency problem, are used in the design to construct the reliable critical datapath. The design targets latch-free and extremely fine-grain or gatelevel pipeline, where the depth of every pipeline stage is only one dual-rail dynamic logic. HSPICE simulation results, in a 65 nm design technology, indicate that the proposed design increases the throughput by 120% and decreases the power consumption by 54% compared with PS0, a classic dual-rail asynchronous pipeline implementation style, in 4-bit wide FIFOs. Moreover, this method is applied to design an array style multiplier. It shows that the proposed design reduces power by 37.9% compared to classic synchronous design when the workloads are 55%. A chip has been fabricated with a 4 × 4 multiplier function, which works well at 2.16G dataset/s (Post-layout simulation).

show abstract

Section: Introductionmentioning

confidence: 99%