Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures

Gangwar, Anup; Balakrishnan, M.; Panda, Preeti Ranjan; Kumar, Anshul

doi:10.1007/s10766-007-0045-2

Cited by 3 publications

(8 citation statements)

References 9 publications

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“…It needs to be noted that the number of cycles and the cycle time itself are two metrics for processor performance. Our further experiments, reported in Gangwar et al [2005], have established that the cycle time is severely limited in the case of unclustered VLIWs as well as RF-to-RF mechanisms, whereas in the case of other interconnects, there is as little as 10% variation in cycle time.…”

Section: Experimental Results and Observationsmentioning

confidence: 65%

“…This is ignoring the latency of such transfers using global buses (assumed bus latency is 1) vis-à-vis local transfers. In a real scenario, the global buses would either be much slower than the rest of the system (multicycle) or pipelined to prevent the system clock period from dropping [Gangwar et al 2005]. Figures 13 and 14 show the average node fanout (ANF) and standard deviation (SD) of this fanout, respectively.…”

Section: Experimental Results and Observationsmentioning

confidence: 99%

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Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures

Gangwar¹,

Balakrishnan

Kumar

2007

ACM Trans. Des. Autom. Electron. Syst.

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VLIW processors have started gaining acceptance in the embedded systems domain. However, monolithic register file VLIW processors with a large number of functional units are not viable. This is because of the need for a large number of ports to support FU requirements, which makes them expensive and extremely slow. A simple solution is to break the register file into a number of smaller register files with a subset of FUs connected to it. These architectures are termed clustered VLIW processors.In this article, we first build a case for clustered VLIW processors with four or more clusters by showing that the achievable ILP in most of the media applications for a 16 ALU and 8 LD/ST VLIW processor is around 20. We then provide a classification of the intercluster interconnection design space, and show that a large part of this design space is currently unexplored. Next, using our performance evaluation methodology, we evaluate a subset of this design space and show that the most commonly used type of interconnection, RF-to-RF, fails to meet achievable performance by a large factor, while certain other types of interconnections can lower this gap considerably. We also establish that this behavior is heavily application dependent, emphasizing the importance of application-specific architecture exploration. We also present results about the statistical behavior of these different architectures by varying the number of clusters in our framework from 4 to 16. These results clearly show the advantages of one specific architecture over others. Finally, based on our results, we propose a new interconnection network, which should lower this performance gap.

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Section: Experimental Results and Observationsmentioning

confidence: 65%

Section: Experimental Results and Observationsmentioning

confidence: 99%

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures

Gangwar¹,

Balakrishnan

Kumar

2007

ACM Trans. Des. Autom. Electron. Syst.

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“…We expect inter-cluster routability issues to appear only in massively parallel architectures with many clusters, which do not match our media application domain. Note, that Gangwar et al [2005] and Parcerisa et al [2005] also report, that the bus-based model underperforms compared to point-to-point networks.…”

Section: Execution Time Performance Density and Energy Consumptionmentioning

confidence: 86%

“…According to Bekooij [2004], a global bus can significantly simplify scheduling for a partially connected VLIW. However, as concluded in Gangwar [2005] and Parcerisa et al [2005], the (global) bus substantially limits the clock frequency. In this study, we focus on point-to-point networks of clusters, but some of our results are also applicable to bus-based clustered architectures.…”

Section: Taxonomy Of Intercluster Communication Modelsmentioning

confidence: 97%

“…Pointto-point networks of clusters contain dedicated connections among clusters (see Figure 2). If some point-to-point connections are merged, we can derive the popular bus-based ICC model [Faraboschi et al 2000;Gangwar et al 2005;Lapinskii et al 2002;Bekooij 2004] (see Figure 3). According to Bekooij [2004], a global bus can significantly simplify scheduling for a partially connected VLIW.…”

Section: Taxonomy Of Intercluster Communication Modelsmentioning

confidence: 99%

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Inter-cluster communication in VLIW architectures

Terechko

Corporaal

2007

ACM Trans. Archit. Code Optim.

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The traditional VLIW (very long instruction word) architecture with a single register file does not scale up well to address growing performance demands on embedded media processors. However, splitting a VLIW processor in smaller clusters, which are comprised of function units fully connected to local register files, can significantly improve VLSI implementation characteristics of the processor, such as speed, energy consumption, and area. In our paper we reveal that achieving the best characteristics of a clustered VLIW requires a thorough selection of an Inter-cluster Communication (ICC) model, which is the way clustering is exposed in the Instruction Set Architecture. For our study we, first, define a taxonomy of ICC models including copy operations, dedicated issue slots, extended operands, extended results, and multicast. Evaluation of the execution time of the models requires both the dynamic cycle count and clock period. We developed an advanced instruction scheduler for all the five ICC models in order to quantify the dynamic cycle counts of our multimedia C benchmarks. To assess the clock period of the ICC models we designed and laid out VLIW datapaths using the RTL hardware descriptions derived from a deeply pipelined commercial TriMedia processor. In contrast to prior art, our research shows that fully distributed register file architectures (with eight clusters in our study) often underperform compared to moderately clustered machines with two or four clusters because of explosion of the cycle count overhead in the former. Among the evaluated ICC models, performance of the copy operation model, popular both in academia and industry, is severely limited by the copy operations hampering scheduling of regular operations in high ILP (instruction-level parallelism) code. The dedicated issue slots model combats this limitation by dedicating extra VLIW issue slots purely for ICC, reaching the highest 1.74 execution time speedup relative to the unicluster. Furthermore, our VLSI experiments show that the lowest area and energy consumption of 42 and 57% relative to the unicluster, respectively, are achieved by the extended operands model, which, nevertheless, provides higher performance than the copy operation model.

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Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors

Kobayashi

Jayapala

Raghavan

et al. 2007

ACM Trans. Des. Autom. Electron. Syst.

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Clustering L0 buffers is effective for energy reduction in the instruction memory hierarchy of embedded VLIW processors. However, the efficiency of the clustering depends on the schedule of the target application. Especially in heterogeneous or data clustered VLIW processors, determining energy efficient scheduling is more constraining.This article proposes a realistic technique supported by a tool flow to explore operation shuffling for improving generation of L0 clusters. The tool flow explores assignment of operations for each cycle and generates various schedules. This approach makes it possible to reduce energy consumption for various processor architectures. However, the computational complexity is large because of the huge exploration space. Therefore, some heuristics are also developed, which reduce the size of the exploration space while the solution quality remains reasonable. Furthermore, we also propose a technique to support VLIW processors with multiple data clusters, which is essential to apply the methodology to real world processors.The experimental results indicate potential gains of up to 27.6% in energy in L0 buffers, through operation shuffling for heterogeneous processor architectures as well as a homogeneous This work is supported by JSPS Grant-in-Aid for JSPS Fellows #17.9887. Based on Kobayashi, Y., Jayapala, M., Raghavan, P., Catthoor, F., and Imai, M. Operation shuffling for low energy L0 cluster generation on heterogeneous VLIW processors.

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Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures

Abstract: Abstract

Cited by 3 publications

References 9 publications

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures

Inter-cluster communication in VLIW architectures

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors

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