Evaluation of current QoS Mechanisms in Networks on Chip

Mello, Ana Maria Lisboa de; Tedesco, Leonel Pablo; Calazans, Ney; Moraes, Fernando

doi:10.1109/issoc.2006.321981

Cited by 20 publications

(10 citation statements)

References 8 publications

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“…In [39], Hansson et al provide the latency and throughput guarantees based on the approach of data flow analysis technique, determining required buffer size at network interfaces, which is applicable to the AEthereal NoC. Many other works have been published with variations over these basic ideas [40], [41], [42], [43], [44], [45], [46], [47], [48], [49].…”

Section: Related Workmentioning

confidence: 99%

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Rahmati

Murali

Benini³

et al. 2013

IEEE Trans. Comput.

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Abstract-Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst case bandwidth and latency bounds for RT traffic streams on wormhole-switched NoCs with arbitrary topology. The proposed methods apply to best-effort NoC architectures, with no extra hardware dedicated to RT traffic support. By applying our methods to several realistic NoC designs, we show substantial improvements (more than 30 percent in bandwidth and 50 percent in latency, on average) in bound tightness with respect to existing approaches.

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Section: Related Workmentioning

confidence: 99%

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Rahmati

Murali

Benini³

et al. 2013

IEEE Trans. Comput.

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“…Marescaux and Corporaal [2007] present a QoS NoC architecture that uses both best effort and guaranteed traffic, but requires specialized hardware and virtual channels. Many works present improvements and variations [Bolotin et al 2004;Bjerregaard and Sparso 2005;Bouhraoua and Elrabaa 2006;Feliciian and Furber 2004;Kavaldjiev et al 2004;Leroy et al 2005;Mello et al 2006;Millberg et al 2004;Mondinelli et al 2004;Mullins et al 2006;Radulescu et al 2005;Rijpkema et al 2003], but all use specialized hardware to provide QoS. A recent survey of NoCs [Salminen 2008] shows that most NoC architectures do not have specialized hardware for QoS and therefore a method to design NoCs that provides guarantees on the delay of communication flows is necessary.…”

Section: Related Workmentioning

confidence: 99%

Designing best effort networks-on-chip to meet hard latency constraints

Seiculescu

Rahmati

Murali³

et al. 2013

ACM Trans. Embed. Comput. Syst.

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Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform experiments on several System on Chip (SoC) benchmarks. We compared against a topology synthesis method with no support for real-time constraints and we show that the proposed method can produce topologies that can meet significantly tighter worst case latency constraints (on average 44%). We also show that the tightest worst case latency can be provided with little overhead on power consumption (on average 8.5%).

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“…In contrast, multiple traffic flows share the same priority or the same resource, thus, could cause unpredictable conditions [53]. The traffic with higher service level is guaranteed in a relative fashion in a connection-less scheme by prioritizing each type of traffic flow.…”

Section: Connection-less Schemementioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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Evaluation of current QoS Mechanisms in Networks on Chip

Cited by 20 publications

References 8 publications

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Designing best effort networks-on-chip to meet hard latency constraints

Networks on Chips: Structure and Design Methodologies

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