Evaluation of Device Fabrication from FET to CFET: A Review

Abstract

Semiconductor industry is advancing day by day to meet the needs of society. As technology grows, the transistor density in an IC increases to augment the performance keeping down the size. Due to the miniaturization of transistors over the past decades, technological progress is in great demand. Vigorous scaling of a planar MOSFET has outaged its nanoscale era due to significant complications associated with increased parasitic capacitance, subthreshold leakage current, thinner gate oxides, which led the researchers to develop and innovate new devices with improved efficiency at low power parameters and reduced short channel effects (SCEs). In this review article, recent technological demand for FETs with multiple gates has been explored and reviewed with advancements. Devices with multiple gates show better performance than conventional FETs due to their steep subthreshold slope, lower leakage current and excellent electrostatic properties even in nanometer regime channel lengths. A triple gate FET and a gate all around FET further improve gate control over the channel. Using FinFET based multi-gate technology, gate control over the channel charge could be increased along with a reduction in parasitic capacitances. To explore the discontinuity of research, the challenges of FinFET technologies have also been addressed along with the introduction of emerging devices. Nanosheets and forksheets address these problems well, as gate structures are stacked on top of each other to form a multiple gate structure that supports enhanced gate control over the channel, whereas C-FET introduces 3D scaling by "folding" the nFET on top of the pFET by exploiting the full edge possibilities of device scaling in 3D.

Steep Slope Field Effect Transistors Based on 2D Materials

“…Main figure of merits that describe SCEs include subthreshold swing (SS), drain induced barrier lower (DIBL), gate leakage, subthreshold voltage (V th ) roll off, punch through and off state current (I off ) DOI: 10.1002/aelm.202300625 increase and the like. [4][5][6][7] SS reflects the transistor's switching ability from on-state to off-state at subthreshold regime, which defines the minimal gate voltage needed for the drain current I DS to increase by one order of magnitude at subthreshold regime, and can be described as,…”