Evaluation of fault attack detection on SRAM-based FPGAs

Benevenuti, Fabio; Kastensmidt, Fernanda Lima

doi:10.1109/latw.2017.7906747

Cited by 8 publications

(12 citation statements)

References 5 publications

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“…The percentage of undetected errors was used to evaluate the error detection capability. In [14], the fault injection results at the configuration memory of a SRAM-based FPGA with different detection mechanisms were divided into four categories: detected unrecoverable error (DUE), silent data corruption (SDC), functional interruption (SEFI) and successful completion (OK). The ratio of each category was discussed and used to evaluate different detection mechanisms.…”

Section: A Previous Workmentioning

confidence: 99%

“…For the cryptographic circuit which is implemented with the countermeasures, we use the security factor to quantitatively evaluate the effectiveness of the countermeasures, i.e., the security of the cryptographic circuit. The security factor denoted by γ quantifies the difference between the actual amount of information leakage and the theoretical amount of information leakage, as shown in (14).…”

Section: B Security Factormentioning

confidence: 99%

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Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks

2019

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The integrated circuits are faced with the threats of fault injection attacks (FIAs), which employ the faulty results and differential fault analysis to retrieve the vital information processed by the circuits. Countermeasures should be taken to protect the circuits against FIAs. This paper proposes a security evaluation method to quantitatively analyze the resistance of block ciphers with a Substitution-Permutation Network structure against FIAs from an information-theoretic perspective. A quantitative security factor is defined based on the amount of information leakage. Specifically, an extended cipher model is proposed to numerically analyze the theoretical amount of information leakage, and an efficient approach is proposed to obtain the actual amount of information leakage. Experiments by applying the quantitative evaluation method to AES circuit validate feasibility, efficiency and scalability of the method. The experimental results show that the security factor can quantify the effects of different fault models and countermeasures. 2000 fault injections are sufficient to complete the evaluation under the considered fault models within 10 microseconds. The proposed method can be used during the circuit design stage as well as chip testing stage.

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Section: A Previous Workmentioning

confidence: 99%

Section: B Security Factormentioning

confidence: 99%

Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks

2019

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“…While two or three redundant copies of the design work correctly, errors will be masked and the output of the block will be correct [4]. In [22], many approaches are used to detect a laser SEU faults for LEON3 on SRAM-based FPGA with the integration of several fault countermeasure techniques, the results obtained show that the modular triplication with single voter is the best one to mask errors. In [23], authors announced that a TMR presents a portable and robust solution.…”

Section: A Principle Of Tmrmentioning

confidence: 99%

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Kchaou¹,

Youssef²,

Tourki³

2017

ijacsa

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“…With respect to the fault duration and intensity, the injected faults can be classified into permanent, persistent, and transient, and into single-bit and multi-bit faults [21]. To resist FIA, countermeasures such as fault detection [5] and hardware redundancy have been explored [14]. However, it is hard to evaluate the effectiveness of the countermeasures until the chip is attacked.…”

Section: Introductionmentioning

confidence: 99%

“…The fault analysis and evaluation analyze the faulty cases of the circuit designs and quantitatively report the performance of the designs against FIAs. The number of faulty outputs caused by FIA was widely used as the evaluation metric [2,5,7]. The information-theory-based method was also proposed to evaluate the security of the encryption systems under DFA [8,28].…”

Section: Introductionmentioning

confidence: 99%

Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs

LiuQiang

TangHonghui

ZhangPeiran

2021

ACM Trans. Des. Autom. Electron. Syst.

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Fault injection attack (FIA) has become a serious threat to the confidentiality and fault tolerance of integrated circuits (ICs). Circuit designers need an effective method to evaluate the countermeasures of the IC designs against the FIAs at the design stage. To address the need, this article, based on FPGA emulation, proposes an in-circuit early evaluation framework, in which FIAs are emulated with parameterized fault models. To mimic FIAs, an efficient scan approach is proposed to inject faults at any time at any circuit nodes, while both the time and area overhead of fault injection are reduced. After the circuit design under test (CUT) is submitted to the framework, the scan chains insertion, fault generation, and fault injection are executed automatically, and the evaluation result of the CUT is generated, making the evaluation a transparent process to the designers. Based on the framework, the confidentiality and fault-tolerance evaluations are demonstrated with an information-based evaluation approach. Experiment results on a set of ISCAS89 benchmark circuits show that on average, our approach reduces the area overhead by 41.08% compared with the full scan approach and by over 20.00% compared with existing approaches. The confidentiality evaluation experiments on AES-128 and DES-56 and the fault-tolerance evaluation experiments on two CNN circuits, a RISC-V core, a Cordic core, and the float point arithmetic units show the effectiveness of the proposed framework.

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Evaluation of fault attack detection on SRAM-based FPGAs

Cited by 8 publications

References 5 publications

Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks

Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs

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