Evaluation of High Speed Hardware Multipliers - Fixed Point and Floating point

Ahmed, Awais; Abbas, Syed; Siddique, Muhammad Faheem; Haider, Hussnain

doi:10.11591/ijece.v3i6.4185

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“…Hwang in [5] implemented complex QR factorization based on Givens rotation for real-time detection of MIMO signal and also several hardware reduction techniques like constant multiplier sharing and look-up table elimination for CORDIC modules were devised. High speed hardware multipliers were evaluated in [6]. Nazar in [7] discussed low complexity hardware architecture for QR decomposition.…”

Section: Introductionmentioning

confidence: 99%

A CORDIC based QR Decomposition Technique for MIMO Detection

Edward¹,

Malarvizhi²

2018

IJECE

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CORDIC based improved real and complex QR Decomposition (QRD) for channel pre-processing operations in (Multiple-Input Multiple-Output) MIMO detectors are presented in this paper. The proposed design utilizes pipelining and parallel processing techniques and reduces the latency and hardware complexity of the module respectively. Computational complexity analysis report shows the superiority of our module by 16% compared to literature. The implementation results reveal that the proposed QRD takes shorter latency compared to literature. The power consumption of 2x2 real channel matrix and 2x2 complex channel matrix was found to be 12mW and 44mW respectively on the state-of-the-art Xilinx Virtex 5 FPGA.

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Section: Introductionmentioning

confidence: 99%