Evaluation of NoC on multi-FPGA interconnection using GTX transceiver

Abstract

Abstract-Multi-FPGA platforms are very popular today for pre-silicon verification of complex designs due to their low cost and high speed. The idea is to divide these systems into smaller sub-systems and implement each one on a separate chip. The challenge is that the number of IOs available on FPGA remains constant despite the technological evolution. This problem is resolved by multiplexing several cut-signals using the time division multiplexing scheduling mechanism. This structure has a strong effect on the speed of transmission between FPGAs. However, an inter-FPGA bottleneck appears. In this paper, we focus on evaluating the Network-on-Chip on multi-FPGA using the high speed serial transceiver GTX block. In order to speed up the transmission between FPGAs, GTX Transceiver is used to provide a high bandwidth while using fewer pins compared to existing approaches based on ordinary FPGA IOs pins. Depending on the available multi-gigabit transceiver, the bandwidth per connection is between 3.125 and 28 Gb/s which allows for large amounts of data to be moved quickly between multiple FPGAs. In our evaluation, a VC707 platform based on the Virtex-7 device is used. The simulation results show that the proposed architecture provides low area consumption and latencies under different traffic patterns.

NoC2: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

“…In this approach, only one centralized module, i.e., a PE or an NI, is used as a gateway between all cores in its system and the Communication Peripheral Controller (CPC) [10,11]. An analogous approach is presented by Dorai et al to alleviate the interfacing burden from PEs and NIs [12]. As such, no centralized gateway PE, or NI, is used and cores within the NoC-based system are allowed to access the CPC in a Time-Division Multiple Access (TDMA) fashion.…”

“…Dorai et al proposed interfacing multi-FPGA NoC-based systems using GTX transceivers [12]. As shown in Figure 3, their proposal embeds a GTX transceiver within each NoC-based system.…”

“…To avoid creating a centralized hotspot in the system, the presented approach employs a distributed buffering method, where a dedicated buffer connects between each individual NI and the CPC. Furthermore, the intra-NoC Figure 3: Interfacing NoC-based systems using GTX transceivers [12].…”

A spread spectrum approach to time-domain near-infrared diffuse optical imaging using inexpensive optical transceiver modules

“…The MGTs of Kintex 7 are called GTX Transceivers and are used as a basic block for common interface protocols (e.g. PCIe and SATA) [ 29 ]. The Kintex 7 FPGA features sixteen GTX ports, which can drive similar Gigabit optical transceiver modules in parallel, and modulate them in a synchronous or asynchronous manner, supporting line speeds from 500Mb/s to 12.5Gb/s.…”