Evaluation of Power Efficient FIR Filter for FPGA based DSP Applications

Bhattacharjee, Subhankar; Sil, Sayantan; Chakrabarti, Amlan

doi:10.1016/j.protcy.2013.12.431

Cited by 16 publications

(10 citation statements)

References 14 publications

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“…In [2], the researchers addressed the different designs of FIR filters, and they concentrated on rate and power consumption. The focus is on the different applications of FIR filters.…”

Section: Background Workmentioning

confidence: 99%

Performance of Improved FIR filer using FPGA

Prasad. K*

2019

IJRTE

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A crucial part of the digital system is the FIR filter where its framework is robust and simple to connect. In this paper, a regular FIR filter and an optimized FIR filter were modeled using window functions. The FIR filter was designed and contrived by FPGA for digital signal filtering. Also in this paper, a regular FIR filter and an optimized FIR filter were built with window usability. The main characteristic of the application is the Xillinx ISE development suite program to build the FPGA data filter accelerator. The paper also simulates the hardware and software co-designed FIR filter and provides simulation findings about hardware assets and variations in quality compared to the standard and improved FIR filter

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“…In [2], the researchers addressed the different designs of FIR filters, and they concentrated on rate and power consumption. The focus is on the different applications of FIR filters.…”

Section: Background Workmentioning

confidence: 99%

Performance of Improved FIR filer using FPGA

Prasad. K*

2019

IJRTE

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“…S. Bhattacharjee, S. Sil, and A. Chakrabarti [16] proposed low-power FIR filter design implementation for DSP applications based on FPGA with the support of Xilinx 6V1X130T1FF1156. In this paper, many forms of the structure were observed and analyzed and they found out that FIR structure took a number of registers and it reduced power consumption.…”

Section: Related Workmentioning

confidence: 99%

Low Cost FPGA Implementation of RFIR Filter Based on a Radix-4 Algorithm

Venkateswarlu¹,

Kumar²

2018

IJIES

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The Reconfigurable Finite Impulse Response (RFIR) filter design is a significant operation in Digital Signal Processing (DSP). The RFIR designs often implemented to evaluate the system performance and hardware utilization. The traditional RFIR filter design depends on more sub module such as subtractions, adders, and shifters, which occupies more area and increase the system complexity. To overcome this problem, a Low Cost-Radix4-RFIR (LC-R4-RFIR) filter design is introduced. This research work designed an efficient RFIR filter with the help of Radix 4 approach, which reduced the filter area and hardware utilization. The RFIR filter was designed by using R4 approach for multiplication operation. Multiplication is the one of the main process of adding a number of Partial Products (PPs) Hence, integer multiplication is implemented in serial parallel mode by employing an accumulator to add these PPs. Using R4, the multiplication operation performed which mitigated the area and hardware utilization of the RFIR design. In Field Programmable Gate Array (FPGA) implementation, the number of Look Up Table (LUT), Slice, flip-flop, area, and frequency calculated for different Virtex devices such as Virtex-6, Virtex-6 Low Power (LP) and Virtex-7. This FPGA experimental results showed that the LC-R4-RFIR filter design performed better compared to conventional FIR filter designs.

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“…This paper achieved higher throughput, but consumes many areas to implement hardware. Subhankar Bhattacharjee [14] introduced the power efficient FIR filter implementation for DSP applications based on FPGA with the support of Xilinx 6V1X130T1FF1156. Several forms of the structures were analyzed and observed that the pipeline FIR filter structure take a number of registers and indirectly it consumes more resources and power.…”

Section: Related Workmentioning

confidence: 99%

Implementation of FIR Filter for Low Power and Area Minimization Using Shift –Add Method without Multipliers

Madugula¹,

Naganjaneyulu²,

Prasad³

2017

IJIES

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Abstract:In VLSI design, performance parameters such as speed and hardware cost are important facts during the implementation of complex algorithms. In this paper, Low Cost Carry SeLect Adder Finite Impulse Response (LC-CSLA-FIR) is introduced to perform the FIR filter operations. With the help of shifter-I, shifter-II, and Shifter-III circuits, the FIR filter operation is performed without using any multipliers. In this new architecture, there is no need of storing the co-efficient in the ROM and number of multipliers. Due to the absence of multipliers, the quantity of hardware is reduced and the performance of the architecture is increase. With the help of Verilog code, the FIR filter architecture is verified in Modelsim software. After Field Programmable Gate Array (FPGA) analysis, Look Up Table (LUT), slices, flip flops, frequency and ASIC implementation area, power, delay, Area Power Product (APP), Area Delay Product (ADP) is improved in LC-CSLA-RFIR method compare to conventional methods.

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Evaluation of Power Efficient FIR Filter for FPGA based DSP Applications

Cited by 16 publications

References 14 publications

Performance of Improved FIR filer using FPGA

Performance of Improved FIR filer using FPGA

Low Cost FPGA Implementation of RFIR Filter Based on a Radix-4 Algorithm

Implementation of FIR Filter for Low Power and Area Minimization Using Shift –Add Method without Multipliers

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