Evaluation of process parameter space of bulk FinFETs using 3D TCAD

Optimal device design of FinFETs on a bulk substrate

“…Generally, we can suppress leakage current in bulk FinFET structure using additional process such as thick isolation oxide (about twice H si ) or substrate doping [4]. However, thick isolation oxide could reduce the effective fin height (controlled by the gate) in a limited fin aspect ratio subject to technology.…”

“…Alternatively, feasibility of using Si-bulk wafers is being sought for the cost of wafers and more importantly for the compatibility with bulk CMOS technology. Due to an issue of substrate leakage (punch-through) in bulk FinFETs, additional substrate doping and isolation oxide are needed [2]- [4]. In this paper, we investigate their impact on performance and propose an optimal yet simple approach.…”

Punch through stop layer optimization in bulk FinFETs

“…Up to now, there have been some comprehensive researches about the PTSL technology for FinFETs [5], and most of the works are based on rectangle-shaped fins. However, in the 1s t mass production of Fin-based technology, Intel resorted to triangle-shaped fins [6].The exact reasons why triangle-shaped fins are used in the products of Intel are unclear, but there are some obvious advantages compared with rectangle-shaped fms, such as 978-1-4799-3282-5/14/$31.00 ©20141EEE better mechanical stability, easier implementation of the process and so forth [7].…”

A pragmatic design methodology using proper isolation and doping for bulk FinFETs

“…A thick gate-tosubstrate isolation oxide also can prevent leakage [8]. The PTS with shallow S/D junction that can suppress leakage and suppress SCEs has also been proposed [9].…”