Evaluation of Signature-Based Testing of RF/Analog Circuits

Zjajo, Amir; Gyvez, José Pineda de

doi:10.1109/ets.2005.22

Cited by 16 publications

(11 citation statements)

References 15 publications

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“…9 shows the tracking of the EVM value for the devices that pass the filter in this case. Alternatively, one can choose to apply some additional structural tests [13][14] to identify outliers in order to avoid retesting indiscriminately all filtered devices. If the fabrication process yield is very high, one could choose to set α = 0.2 which guarantees a low yield loss.…”

Section: Resultsmentioning

confidence: 99%

Defect Filter for Alternate RF Test

Stratigopoulos

Mir

Acar

et al. 2009

2009 14th IEEE European Test Symposium

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Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction of the filter does not require a defect dictionary and can accommodate any underlying density without needing any prior knowledge regarding its parametric form.

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Section: Resultsmentioning

confidence: 99%

Defect Filter for Alternate RF Test

Stratigopoulos

Mir

Acar

et al. 2009

2009 14th IEEE European Test Symposium

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“…For further fault diagnosis and calibration of the analog RF front-end blocks, special circuits have been constructed to measure supply current variations with minimal interference [17] and to calibrate bias currents [18]. It was also demonstrated in [2] that fault coverage can be improved by applying a ramp signal at the power supply nodes to measure the quiescent currents of the devices in different operating regions.…”

Section: B Defect-oriented and Structural Test Approachesmentioning

confidence: 99%

“…In the past as well as in recent projections, it has been reported that testing can contribute up to 40-50% of the total integrated circuit manufacturing cost [1][2][3]. With the advent of more complex and costly system-in-a-package (SIP) and multichip module (MCM) technologies, there is an increased incentive for known-good-die testing at wafer sort to avoid the rising cost of subsequent packaging and final test.…”

Section: Introductionmentioning

confidence: 99%

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Onabajo

Fernández

Silva-Martínez

et al. 2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

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This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in selftest (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present test cost reduction requirements and techniques from a circuit design perspective. One promising approach for the test of fully-integrated RF transceiver front-ends with on-chip loopback and strategically placed power detectors along the RF signal path will be discussed as a demonstrative example of the presented concepts. The main focus in this paper is on reported work that is relevant to improvement of test coverage and cost reduction for on-wafer functional test with minimal area overhead and test time.

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“…Thus, the resistance of the R_pogo pin is changed from 0.1 Ω to 1 kΩ to represent the scenario when the pogo pin is opened because of poor contact. Applying Agilent ADS simulator to the emulation approach [(1) and (2) in Fig. 5a] under normal operation (circuit biased at 3 V with no ESD or contact issues), Fig.…”

Section: Numerical Validationmentioning

confidence: 99%

Enhancement of radio frequency device's contact test using a novel method

Chen²,

Ko³

2014

IET Science, Measurement & Technology

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This investigation describes novel automatic test equipment for verifying the electric contact of radio frequency (RF) traces between RF devices by, for example, the opens and shorts test. An equivalent circuit for modelling the RF device incorporating RF traces with contact impedance is applied for theoretical analysis of the prototype design. The effectiveness of the proposed novel test methodology is then validated. The measured data from experimental testing of RF devices attained in production runs precisely address the contact issue using the novel methodology presented here.

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Evaluation of Signature-Based Testing of RF/Analog Circuits

Cited by 16 publications

References 15 publications

Defect Filter for Alternate RF Test

Defect Filter for Alternate RF Test

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Enhancement of radio frequency device's contact test using a novel method

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