Evaluation of the statistical delay quality model

Sato, Y.; Hamada, Shuji; Maeda, Toshiyuki; Takatori, A.; Kajihara, Seiji

doi:10.1109/aspdac.2005.1466179

Cited by 36 publications

(28 citation statements)

References 12 publications

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“…SDQL takes into account a delay defect distribution y = F (s), where s is the defect size and F (s) is the probability of SDDs [11], F (s) is a exponential distributions and can be expressed as:…”

Section: B Statistical Delay Quality Level (Sdql)mentioning

confidence: 99%

“…Statistical delay quality level is a metric to quantitatively estimate the delay quality by measuring the test escape rate of delay defects [11]. SDQL takes into account a delay defect distribution y = F (s), where s is the defect size and F (s) is the probability of SDDs [11], F (s) is a exponential distributions and can be expressed as:…”

Section: B Statistical Delay Quality Level (Sdql)mentioning

confidence: 99%

“…Then, we generate test patterns with the commercial timing-aware ATPG flow to screen small delays faults induced by defective TSVs. We evaluate the quality of the patterns through delay effectiveness (DE) and the statistical delay quality level (SDQL) [11].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Timing-aware ATPG for critical paths with multiple TSVs

Metzler

Todri‐Sanial

Bosio

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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International audienceThrough-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools

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Section: B Statistical Delay Quality Level (Sdql)mentioning

confidence: 99%

Section: B Statistical Delay Quality Level (Sdql)mentioning

confidence: 99%

See 1 more Smart Citation

Timing-aware ATPG for critical paths with multiple TSVs

Metzler

Todri‐Sanial

Bosio

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

View full text Add to dashboard Cite

show abstract

“…This means that the majority of devices that fail due to delay defects fail due to small delay defects [2]. Detection of these defects can be missed by typical and advanced test methodologies and can result in test escapes [3,4]. These defects can degrade with use leading to a reliability risk [1,5,6].…”

Section: Introductionmentioning

confidence: 99%

Screening small-delay defects using inter-path correlation to reduce reliability risk

Garcia-Gervacio

Nocua

Champac

2015

Microelectronics Reliability

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“…Modern chips are becoming more vulnerable to small delay defects (SDD) due to the scaling of the manufacturing technology and the increase in clock frequencies [1] [2]. Timing-aware ATPG, which tries to activate and propagate fault effects through long paths, is a solution to addressing the deficiency of the gross delay fault model.…”

Section: Introductionmentioning

confidence: 99%

GPU-based timing-aware test generation for small delay defects

Liao

Chen

Lin

et al. 2014

2014 19th IEEE European Test Symposium (ETS)

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A GPU-based timing-aware ATPG is proposed to generate a compact high-quality test set. The test generation algorithm backtraces and propagates along multiple long paths so that many test patterns are generated at the same time. Generated test patterns are then fault simulated and selected. Compared with an 8-core CPU-based timing-aware commercial ATPG, the proposed GPU-based technique achieved 36% test length reductions on large benchmark circuits while the SDQL quality remains almost the same.

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Evaluation of the statistical delay quality model

Cited by 36 publications

References 12 publications

Timing-aware ATPG for critical paths with multiple TSVs

Timing-aware ATPG for critical paths with multiple TSVs

Screening small-delay defects using inter-path correlation to reduce reliability risk

GPU-based timing-aware test generation for small delay defects

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