Evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3D system integration

Abstract

In this paper we describe the process integration of a temporary wafer handling system for wafer thinning and thin wafer backside processing. Thin wafer handling is a key technology and enabler for the wafer level fabrication of through silicon via (TSV) based 3D architectures. The work was done as evaluation study to prove the compatibility of a thin wafer handling system with standard processes used for thinning and backside processing of "via-first" TSV wafers as well as for thinning of bumped wafers. The used thin wafer handling system is based on perforated carrier wafers, which are bonded by an adhesive to the customer wafer and de-bonded by solvent release of the adhesive. All wafers used in this work had 200 mm format. The evaluation was run systematically in three major phases. In the first phase the main process scenarios, which require thin wafer handling, were defined. In a second phase setup trials for bonding, thinning, backside processing and debonding we re run on monitor wafers with different types of front side topography, but without TSVs. After finishing the setup trials in a third phase, the monitor wafers were replaced by wafers with copper filled TSVs, which were fabricated in "via-first" technology. Using the established thin wafer handling and processing sequence, silicon interposer wafers with 55 m thickness were manufactured. The measured via chains have via pitches of 28 m using 15 m via diameter

Prospects and limits in wafer-level-packaging of image sensors

“…TTVs of ±2,5µm are obtainable with an adequate bonding process using a thin glue layer. In other experiments we observed, that with increasing bonding layer thickness, the TTV of the device wafer after thinning goes up as well [5].…”

Wafer level 3D system integration based on silicon interposers with through silicon vias

“…release by laser ablation of glue through transparent carrier wafers [8,9] 2. release by glue dissolution with solvent through perforated carrier wafers [10,11] 3. mechanical release by slide-off at elevated temperatures due to low viscosity of glue [12,13] 4. mechanical release by tilting due to low adhesion of glue at bond interface [14,15] The suitable temporary carrier solution needs to be chosen carefully depending on the complexity of backside processing, the kind of front side topography and the kind of the final assembly method. In each case, the chosen carrier solution needs to be highly flexible in use and robust to give an optimal support for the corresponding thin wafer processing and handling task.…”

Substrate-Influenced Thermo-Mechanical Fatigue of Copper Metallizations: Limits of Stoney’s Equation

“…Thereby, the criterion, h * = h f / h s is not strictly defined, but rather arbitrarily chosen (often set to h * = 0.01, see [ 6 ]). In modern microelectronics, increasing product performance requires thinner and thinner substrates to decrease the vertical resistance and device volume, while keeping the metallization thicknesses similar [ 8 , 9 ]. In literature, numerous studies report the effect of film thickness on microstructural changes [ 10 , 11 , 12 ], but experimental work dealing with the influence of substrate thickness is very limited.…”