EvoApprox8b:  Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods

Mrázek, Vojtěch; Hrbáček, Radek; Vašíček, Zdeněk; Sekanina, Lukáš

doi:10.23919/date.2017.7926993

Cited by 239 publications

(207 citation statements)

References 14 publications

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“…2 correspond to circuits with different trade-offs between WCE in % and the power-delay product (PDP 2 ), which is a key non-functional circuit characteristic. These circuits were obtained using various existing approaches including: (M1) configurable circuits from the lpACLib library [17], (M2) the bit-significance-driven logic compression [15], (M3) the bit-width truncation [10], (M4) compositional techniques [11], and (M5) circuits from the EvoApproxLib library [13]. We can see that just the bit-width truncation can provide a quality of results comparable with ADAC (in terms of the PDP reduction for the given WCE), but for large target errors (20% WCE or more) only.…”

Section: Evaluation Related Work and Applicationsmentioning

confidence: 99%

ADAC: Automated Design of Approximate Circuits

Češka

Matyas

Mrázek

et al. 2018

Computer Aided Verification

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Abstract. Approximate circuits with relaxed requirements on functional correctness play an important role in the development of resourceefficient computer systems. Designing approximate circuits is a very complex and time-demanding process trying to find optimal trade-offs between the approximation error and resource savings. In this paper, we present ADAC-a novel framework for automated design of approximate arithmetic circuits. ADAC integrates in a unique way efficient simulation and formal methods for approximate equivalence checking into a search-based circuit optimisation. To make ADAC easily accessible, it is implemented as a module of the ABC tool: a state-of-the-art system for circuit synthesis and verification. Within several hours, ADAC is able to construct high-quality Pareto sets of complex circuits (including even 32-bit multipliers), providing useful trade-offs between the resource consumption and the error that is formally guaranteed. This demonstrates outstanding performance and scalability compared with other existing approaches.

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Section: Evaluation Related Work and Applicationsmentioning

confidence: 99%

ADAC: Automated Design of Approximate Circuits

Češka

Matyas

Mrázek

et al. 2018

Computer Aided Verification

Self Cite

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“…In order to evaluate the population, each candidate solution is evaluated using the so-called fitness function. As the problem is in principle multi-objective (error versus power consumption or area), a suitable multi-objective optimization algorithm has to be taken [2], [3]. While the circuit area on a chip can be easily estimated by summing the areas of components involved in the circuit, the error computation is more time demanding (see next sections).…”

Section: Evolutionary Approximationmentioning

confidence: 99%

“…While the aim of general-purpose approximation methods (e.g. SALSA [9], AXILOG [10], ASLAN [11], ABA-CUS [12], CGP [2], [3]) is to automatically approximate any circuit regardless of its structure, the circuit-specific methods are focused on a rather specific class of circuits (such as adders or multipliers [4]). …”

Section: Approximate Computingmentioning

confidence: 99%

“…Unfortunately, the quality of approximation methods has been compared in the literature only rarely (see a survey of associated methodological problems in [2]); in most cases only parameters of approximate adders and multipliers were compared [4]. In this paper, we compare two approximation strategies based on CGP applied to approximate various common implementations of the median filter.…”

Section: Introductionmentioning

confidence: 99%

“…In our previous work, we have developed circuit approximation methods [2], [3] based on Cartesian genetic programming (CGP) which is a branch of evolutionary algorithms capable of designing and optimizing digital circuits.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter

Sekanina¹,

Vašíček²,

Mrázek³

2017

RADIOENGINEERING

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Low power and area efficient error tolerant adder for image processing application

Priyadharshni

Sundaram

2020

Circuit Theory & Apps

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Approximate computing-based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1-bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16-bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05×10 −5 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal-to-noise ratio (PSNR). KEYWORDSapproximate carry select adder, approximate computing, approximate full adder, imprecise full adder, error tolerant adder Int J Circ Theor Appl. 2020;48:696-708. wileyonlinelibrary.com/journal/cta

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EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods

Cited by 239 publications

References 14 publications

ADAC: Automated Design of Approximate Circuits

ADAC: Automated Design of Approximate Circuits

Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter

Low power and area efficient error tolerant adder for image processing application

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