Evolution of low frequency noise and noise variability through CMOS bulk technology nodes

Ioannidis, Eleftherios; Haendler, S.; Bajolet, A.; Rosa, J.; Manceau, Jean-Philippe; Dimitriadis, C. A.; Ghibaudo, G.

doi:10.1109/icnf.2013.6578985

Cited by 12 publications

(13 citation statements)

References 8 publications

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“…This trend is confirmed for a wide range of CMOS technology nodes between 0.12 μm and 20 nm ( Figure 5). Indeed, this figure shows the standard deviation of the logarithm of the normalized draincurrent noise versus the inverse of the square root of the device area for nMOS and pMOS transistors from six different technology nodes, that is, 0.12, 90 nm, 65 nm, 45 nm, 28 nm and 20 nm with gate oxide thicknesses between 8.5 and 1.3 nm [15]. The results revealed that the volumetric trap density for both nMOS and pMOS devices increases as the technology nodes are developed from 0.5 μm to 20 nm.…”

Section: C-noise Variability In Sio 2 Sion and High-k/metal Gate CMmentioning

confidence: 99%

Modeling of low‐frequency noise in advanced CMOS devices

Ghibaudo

Jomaah

2015

Int J Numerical Modelling

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The modeling and characterization of low-frequency noise and noise variability in various regimes of operation are investigated for the main advanced complementary metal-oxide semiconductor (CMOS) technologies. Novel materials and innovative device architectures from 0.5 μm to 20 nm gate lengths are studied. The impact of gate stack, realized with ultrathin oxides, polysilicon gate and high-k/metal gate is analyzed. The influence of alternative channel materials, in particular ultrathin body silicon-on-insulator layers, strain Si and III-V materials is addressed. The comparison of low-frequency noise in advanced device architectures, including bulk Si, fully depleted SOI, FinFET, junctionless, and multi-gates structures, is shown. Accurate noise models, taking into account the main physical mechanisms, are proposed for all these very advanced technologies, which will be needed for the nanoelectronics of the next decade.

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Section: C-noise Variability In Sio 2 Sion and High-k/metal Gate CMmentioning

confidence: 99%

Modeling of low‐frequency noise in advanced CMOS devices

Ghibaudo

Jomaah

2015

Int J Numerical Modelling

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“…Recent deep submicron technologies increase defective components, mainly due to process variability [1], electromagnetic interferences, charge injection or radiation [2], or even cross talk effect [3]. Therefore, it is essential to provide support for dynamic faults using a circuit that detects and corrects faults, and additionally providing statistics to a high-level layer (e.g.…”

Section: Introductionmentioning

confidence: 99%

A fault prediction module for a fault tolerant NoC operation

Silveira

Bodin

Ferreira

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

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Each new production technology of integrated circuit (IC) drives more transistors area reduction, implying smaller and denser circuits. This scenario allows integrating several Processing Elements (PEs) into the same IC with efficient communication architecture such as the scalable topologies of Network on Chip (NoC). However, these newer production technologies introduce more defects in various parts of the IC that have to be detected and well corrected to prevent malfunction of the IC. This work presents the Fault Prediction Module (FPM), which presents low area consumption and a power circuit based on thresholds enabling to detect link quality, i.e. operating properly, operating with fault tendency or with permanent fault. Additionally, we show how to tune the FPM threshold parameter aiming to use this circuit as a mechanism with comprehensive fault model. The set of experimental results shows the effectiveness of our proposal.

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“…Recent submicron technologies provide more process variability increasing the quantity of defective components [2]. A defective router or link may ruin the mesh communication structure leading to an irregular topology (i.e.…”

Section: Introductionmentioning

confidence: 99%

Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs

Silveira

Marcon

Cortez

et al. 2015

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

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Newest processes of CMOS manufacturing allow integrating billions of transistors in a single chip. This huge integration enables to perform complex circuits, which require an energy efficient communication architecture with high scalability and parallelism degree, such as a Network-on-Chip (NoC). However, these technologies are very close to physical limitations implying the susceptibility increase of faults on manufacture and at runtime. Therefore, it is essential to provide a method for efficient fault recovery, enabling the NoC operation even in the presence of faults on routers or links, and still ensure deadlock-free routing even for irregular topologies. A preprocessing approach of the most probable fault scenarios enables to anticipate the computation of deadlock-free routings, reducing the time necessary to interrupt the system operation in a fault event. This work describes a preprocessing technique of fault scenarios based on forecasting fault tendency, which employs a fault threshold circuit and a high-level software that identifies the most relevant fault scenarios. We propose methods for dissimilarity analysis of scenarios based on measurements of cross-correlation of link fault matrices. At runtime, the preprocessing technique employs analytic metrics of average distance routing and links load for fast search of sound fault scenarios. Finally, we use RTL simulation with synthetic traffic to prove the quality of our approach.

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Evolution of low frequency noise and noise variability through CMOS bulk technology nodes

Abstract: Th-P-28International audienc

Cited by 12 publications

References 8 publications

Modeling of low‐frequency noise in advanced CMOS devices

Modeling of low‐frequency noise in advanced CMOS devices

A fault prediction module for a fault tolerant NoC operation

Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs

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