Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network Architecture

Gong, Jicheng; Yang, Ming

doi:10.1109/tevc.2017.2779874

Cited by 23 publications

(8 citation statements)

References 27 publications

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“…On the basis of subshot segmentation, key frames are extracted. e subshot is regarded as a fully connected graph, the frame is regarded as the vertex of the graph, and the frame difference is regarded as the edge of the connected vertex [12,13]. In this way, the problem of key frame extraction can be transformed into the problem of finding the center of a fully connected graph.…”

Section: Key Frame Extraction Based On a Fully Connectedmentioning

confidence: 99%

An Online Arrangement Method of Difficult Actions in Competitive Aerobics Based on Multimedia Technology

Li¹

2021

Security and Communication Networks

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In accordance with the development trend of competitive aerobics’ arrangement structure, this paper studies the online arrangement method of difficult actions in competitive aerobics based on multimedia technology to improve the arrangement effect. RGB image, optical flow image, and corrected optical flow image are taken as the input modes of difficult action recognition network in competitive aerobics video based on top-down feature fusion. The key frames of input modes in competitive aerobics video are extracted by using the key frame extraction method based on subshot segmentation of a double-threshold sliding window and fully connected graph. Through forward propagation, the score vector of video relative to all categories is obtained, and the probability score of probability distribution is obtained after normalization. The human action recognition in competitive aerobics video is completed, and the online arrangement of difficult action in competitive aerobics is realized based on this. The experimental results show that this method has a high accuracy in identifying difficult actions in competitive aerobics video; the online arrangement of difficult actions in competitive aerobics has obvious advantages, meets the needs of users, and has strong practicability.

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Section: Key Frame Extraction Based On a Fully Connectedmentioning

confidence: 99%

An Online Arrangement Method of Difficult Actions in Competitive Aerobics Based on Multimedia Technology

Li¹

2021

Security and Communication Networks

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“…Generally, the reconfigurable platforms used for EHW research include field programmable transistor array (FPTA), field programmable analog array (FPAA), and the most commonly used FPGA [13]. The platform has an important impact on the scale and efficiency of evolution.…”

Section: A Reconfigurable Platformmentioning

confidence: 99%

“…In [25], two cascaded FPAAs were used to create an ANN layer for the hardware evolution of in-situ robotic fault-recovery. Recently, research on ANN-based VRC was discussed in [13], mainly using an improved VRC to optimize evolutionary fault tolerance methods. This report was based on the extrinsic evolution of a Xilinx Virtex SRAM-based FPGA.…”

Section: B Vrc-based Reconfigurable Architecturementioning

confidence: 99%

Hardware Evolution Based on Improved Simulated Annealing Algorithm in Cyclone V FPSoCs

et al. 2020

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Evolvable hardware (EHW) is an emerging area of research that uses evolutionary algorithms (EAs) to construct circuits without manual intervention. However, this technique confronts two major issues: the evolution efficiency of structures and the computational efficiency of EAs. To address these issues, we construct a novel virtual reconfigurable circuit (VRC) based on artificial neural network (ANN) architecture and develop a promising EA based on improved simulated annealing (ISA) for the research of EHW. Here, ISA escapes the local optimization through an inner loop and expands new search space through an outer loop. Furthermore, several strategies are proposed for the representation, perturbation and selection of solutions (individuals) to reduce the computational burden throughout the entire evolution process. The use of an Intel Cyclone V field programmable system-on-chip (FPSoC) further accelerates the execution of the algorithm and provides designers with much more high-level processing power than that provided by soft-cores. The obtained results show that the proposed method achieves high-speed processing and improves computational efficiency. The results also show that the method has good flexibility and scalability. INDEX TERMS Evolvable hardware, artificial neural networks, improved simulated annealing, algorithm design and analysis, FPSoC.

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“…In VRC method, a virtual reconfigurable hardware layer is built upon a specific programmable device, such as FPGA, forming a programmable architecture for EHW. 20 It allows designers to directly access configuration bits for fast reconfiguration. Furthermore, granularity and configuration schema of new VRC architecture can exactly reflect the requirements of a given application.…”

Section: Vrc Architecturementioning

confidence: 99%

“…In VRC method, a virtual reconfigurable hardware layer is built upon a specific programmable device, such as FPGA, forming a programmable architecture for EHW 20 . It allows designers to directly access configuration bits for fast reconfiguration.…”

Section: The Vrc Architecture Based On Fpsoc For Evolving Combinationmentioning

confidence: 99%

On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm

Shang

Chen

Peng

2019

Concurrency and Computation

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This paper presents the on-chip evolution system of combinational logic circuits by a new hybrid algorithm known as improved genetic-simulated annealing algorithm (IGASA). IGASA is based on the concept and principles of genetic algorithm (GA) and simulated annealing (SA). The main idea is to combine GA's global search ability with the advantage of SA's fast convergence to reach an optimal solution. In this paper, a new mutation operation and a repeated annealing (RA) process are introduced to overcome the premature convergence of the standard GA and the large number of searches in the later period. An elitist strategy to enhance convergence characteristic of the proposed algorithm is incorporated to better speed up the evolution process. In addition, the new algorithm is implemented in a new evolvable platform using Intel Cyclone V FPGA with an embedded ARM microprocessor. Comparison of the performance of the improved algorithm to the pure GASA algorithm and standard GA is presented on a number of case studies. The experiment results demonstrate that feasible circuits are always achieved by the IGASA algorithm unlike with other algorithms and the number of generations required is less. KEYWORDS ARM processor, combinational logic circuits, evolvable hardware (EHW), field programmable system-on-chip (FPSoC), improved genetic-simulated annealing (IGASA) 1 INTRODUCTION Evolvable hardware (EHW) is a thriving area of research which uses the genetic algorithm (GA) to construct novel circuits without manual engineering. 1 It is also a new field at the confluence of reconfigurable devices, autonomous systems, artificial intelligence, and automatic design. 2 A complete hardware evolution system usually consists of two main elements: evolutionary algorithm (EA) 3 and reconfigurable hardware device. Specifically, EHW is generally classified into two major classes: extrinsic EHW 4 and intrinsic EHW. 5 The biggest difference between extrinsic EHW and intrinsic EHW is whether the chromosome is evaluated by software simulation or in hardware. In recent years, the emergence of Field Programmable System-on-Chips (FPSoCs) 6 has brought hardware evolution to a third dimension, called On-chip evolution. 7 The FPSoC implements the entire EHW system from a single chip by providing embedded processors (such as ARM cores). By constructing a virtual reconfigurable circuit (VRC) 8 layer, the problem of reconfiguration limitations of commercial FPGA can be well overcome. FPSoCs allow power consumption and board size to be reduced, and reliability and performance (thanks to on-chip communications) to be increased compared to external multichip solutions. 9 However, despite the potential advantages of the FPGA-ARM single-chip platform, the need for designers to have good knowledge and expertise in both hardware and software domains makes this area of research reported in very few works, 10 and all of those works only targeting Xilinx Zynq-7000 devices. 11 Therefore, in order to analyze the detailed performance of different FPSoCs that evolve ...

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Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network Architecture

Cited by 23 publications

References 27 publications

An Online Arrangement Method of Difficult Actions in Competitive Aerobics Based on Multimedia Technology

An Online Arrangement Method of Difficult Actions in Competitive Aerobics Based on Multimedia Technology

Hardware Evolution Based on Improved Simulated Annealing Algorithm in Cyclone V FPSoCs

On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm

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