Exact inductive parasitic extraction for analysis of IGBT parallel switching including DCB-backside eddy currents

Gutsmann, B.; Mourick, P.; Silber, D.

doi:10.1109/pesc.2000.880496

Cited by 25 publications

(4 citation statements)

References 4 publications

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“…R S ≈ 0 Ω, which reduces the original L DS to (1-k 2 )L DS . In fact, the backside metallization of the DBC substrate will also have a similar effect, as reported by [10]. The copper, however, does not provide the optimal damping effect based on the analysis in this paper.…”

Section: B Potential Improvements On the Coupling Coefficientsupporting

confidence: 64%

Exploration of a switching loop snubber for parasitic ringing suppression

Chen

Yao

Boroyevich

et al. 2014

2014 IEEE Energy Conversion Congress and Exposition (ECCE)

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This paper presents the concept of a switching loop snubber that suppresses the device's parasitic ringing by inserting a damping loop that is closely coupled with the original switching loop. The proposed snubber circuit damps only the high-frequency oscillations during the switching transients without either lowering the switching speed or increasing the conduction loss. The operation principle of the circuit is analyzed and experimentally verified. Its potential implementation in an integrated power module is also presented and discussed.

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Section: B Potential Improvements On the Coupling Coefficientsupporting

confidence: 64%

Exploration of a switching loop snubber for parasitic ringing suppression

Chen

Yao

Boroyevich

et al. 2014

2014 IEEE Energy Conversion Congress and Exposition (ECCE)

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“…However, the dynamic current may not be balanced during the switching transient. Asymmetrical parasitic inductance among paralleled dies both in power loop and gate loop can result in significant current imbalance [83][84][85]. Consequently, the dies with higher switching loss tend to have shorter lifetime than other dies, limiting the lifetime of the power module.…”

Section: ) Power Module With Multi-diesmentioning

confidence: 99%

Overview of high voltage sic power semiconductor devices: development and application

Zhang

Wang

2017

Trans. Electr. Mach. Syst.

154

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Research on high voltage (HV) silicon carbide (SiC) power semiconductor devices has attracted much attention in recent years. This paper overviews the development and status of HV SiC devices. Meanwhile, benefits of HV SiC devices are presented. The technologies and challenges for HV SiC device application in converter design are discussed. The state-of-the-art applications of HV SiC devices are also reviewed. Index Terms-High voltage, SiC power semiconductor devices, SiC-based converter.Recently, the emerging HV SiC devices demonstrate the promising performance in terms of high voltage rating, low specific on-resistance and fast switching speed [56]. This section focuses on the characteristics of HV SiC devices versus their Si counterparts. A. Comparison to SiRecent breakthroughs in wide band gap (WBG) SiC material and fabrication technology have led to the development of high

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“…Because optimisation processes lead to changes in geometry it seems appropriate to extract parameters of parts of the assembly independently from all the rest.In [5] the influence of inductive parasitics including the backside baseplate of a module thus involving backside eddycurrents on switching of IGBTs is investigated. Therefor PEEC method (Partial Element Equivalent Circuit) is used giving solution of exact inductances for the example geometry considered.…”

Section: A Peec Model Approachmentioning

confidence: 99%

Interaction between thermal impedance and parasitics in power sections

Förster

Lindemann

2008

2008 13th International Power Electronics and Motion Control Conference

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Considerations refer to thermal optimisation and its coherence with the appearance of electrical parasitics in power electronic systems. Analytical and finite element simulation assisted analysis of thermal resistance depending on geometry of layered assemblies is discussed. Resulting approach provides a basis for considerations on parasitics applying partial element equivalent circuit method (PEEC).

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Exact inductive parasitic extraction for analysis of IGBT parallel switching including DCB-backside eddy currents

Cited by 25 publications

References 4 publications

Exploration of a switching loop snubber for parasitic ringing suppression

Exploration of a switching loop snubber for parasitic ringing suppression

Overview of high voltage sic power semiconductor devices: development and application

Interaction between thermal impedance and parasitics in power sections

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