In this paper, the full flexible performance characterization of a transistor with series inductive/parallel capacitive feedback is carried out in terms of LNA applications. For this purpose, the input VSWR V in -maximum available gain G Tmax variations are constructed for a high technology low-noise transistor that is subject to the required noise figure F req (f ) F min (f ) along the device's operation band depending on the feedback. These V in -G Tmax variations result in the application of a design chart that indicates which value of feedback can be applied within which region of the operation band with the improvable trade-off between the V in and output VSWR V out for the Freq(f) ≥ Fmin(f). Following this, the optimum trade-off between V in and V out is made for the necessary operation frequency regions using the load impedance Z L as an instrument with the predetermined source impedance Z S . Finally, the LNA applications of a series inductive/parallel capacitive feedback applied transistor with the optimum V in , V out , and G T subject to Freq(f) ≥ Fmin(f) ≥ are also presented as distributed across the entire bandwidth in the different operation bands. It can be concluded that this rigorous work will enable a designer to utilize the entire operation frequency band of transistor through using only a single series inductive/parallel capacitive feedback for the LNA designs of Freq(f) ≥ Fmin(f) with the optimum trade-offs among its performance measures.
K E Y W O R D Sfeedback, gain, microwave transistor, noise figure, stability, VSWR
| INTRODUCTIONA low-noise amplifier (LNA) is the most significant part of data transmission systems since its noise dominates the overall sensitivity of the system. The challenge involved in LNA design optimization lies in enabling the transistor to amplify subject to its physical limitations and the trade-off relations among the noise, gain, and mismatching at its input and output ports within the operation domain (V DS , I DS , f). Therefore, the most significant ingredient of an LNA design optimization is the feasible design target space (FDTS), which covers the full potential performance of the transistor in question within its operation (V DS , I DS , f) domain. The FDTS must be calculated through the following two stages: (a) the signal and noise parameters of the transistor are modelled throughout its operation domain (V DS , I DS , f) using either artificial intelligence tools 1-4 or novel optimization methods such as those adopted in 5-7 ; (b) in the second *Corrections added on 08 January 2020, after first online publication: Missing symbols "" and "" throughout the paper have been added.