Excellent 22FDX Hot-Carrier Reliability for PA Applications

Chen, T.; Zhang, C.; Arfaoui, W.; Bellaouar, A.; Embabi, S.H.K.; Bossu, G.; Siddabathula, M.; Chew, Kok Wai; Ong, Suan Ee; Mantravadi, M.K.; Barnett, K.; Bordelon, J.; Taylor, Richard; Janardhanan, Sindhu

doi:10.1109/rfic.2019.8701760

Cited by 29 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The simulated maximum gate-source voltage during the ramp-up of 5V supply is <420mV which is lower than 0.88V. The corresponding maximum gate-drain (<850mV) and drain-source voltages(<820mV) during this simulation are also well below the maximum limit (2.4V) at which they can be used [36]. Because of the isolation between the D/S and back-gate terminals of the transistors in the FDSOI technology, there is no risks of the forward-bias diode formation like that in a bulk process.…”

Section: Biasingmentioning

confidence: 81%

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-V_p-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

Bhat

Zee

Nauta

2022

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

In this article, we propose a CMOS active balun targeting high linearity up to high voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of this active balun are derived using a common highly linear building block (HLBB). The HLBB is designed using an inverter with strong source degeneration. To increase the linearity of this HLBB further, its nonlinearity mechanisms are analyzed in detail. A bootstrapping technique is included in the HLBB to reduce the dominant nonlinearity. Furthermore, a pre-distortion technique cancels most of the non-linearity of the output driving stages. All the linearization techniques proposed are robust to PVT changes. The measured results of the active balun realized on chip in a 22-nm FDSOI CMOS shows < −44-dBc HD3 up to 1.5-Vp−p output swing over 0.01-5.4-GHz. The measured gain and phase errors of the balun action are less than 0.5dB and ±5 • respectively. The chip is powered from a 5V supply and dissipates 925mW.

show abstract

Section: Biasingmentioning

confidence: 81%

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-V_p-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

Bhat

Zee

Nauta

2022

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…In addition, the size was large partly due to the PAE enhancing stack resonators. A differential 3-stack with 22 nm CMOS SOI [13] provides very good output power with a comparable PAE but smaller gain, whereas a differential 2-stack using a 22 nm CMOS SOI [23] shows a very good efficiency, gain and 1 dB compression point, but due to the low VDD, the output power is not comparable to 3 or 4-stack PAs. A differential 2-stack [24,25] implemented using a 28 nm bulk CMOS also shows very high efficiency with a comparable gain and linearity but smaller output power and larger size.…”

Section: Comparison Of the Measured Resultsmentioning

confidence: 99%

Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

et al. 2021

View full text Add to dashboard Cite

This paper presents a fully integrated, four-stack, single-ended, single stage power amplifier (PA) for millimeter-wave (mmWave) wireless applications that was fabricated and designed using 45 nm complementary metal oxide semiconductor silicon on insulator (CMOS SOI) technology. The frequency of operation is from 20 GHz to 30 GHz, with 13.7 dB of maximum gain. The maximum RF (radio frequency) output power (Pout), power-added efficiency (PAE) and output 1 dB compression point are 20.5 dBm, 29% and 18.8 dBm, respectively, achieved at 24 GHz. The error vector magnitude (EVM) of 12.5% was measured at an average channel power of 14.5 dBm at the center of the the 3GPP/NR (third generation partnership project/new radio) FR2 band n258—i.e., 26 GHz—using a 100 MHz 16-quadrature amplitude modulation (QAM) 3GPP/NR orthogonal frequency division modulation (OFDM) signal.

show abstract

“…The simulated maximum gate-source voltage during the ramp-up of 5V supply is <420mV which is lower than 0.88V. The corresponding maximum gate-drain (<850mV) and drain-source voltages(<820mV) during this simulation are also well below the maximum limit (2.4V) at which they can be used [149]. Because of the isolation between the D/S and back-gate terminals of the transistors in the FDSOI technology, there is no risks of the forward-bias diode formation like that in a bulk process.…”

Section: Biasingmentioning

confidence: 81%

Wide band linearization techniques for RF receiver front-ends

Bhat

View full text Add to dashboard Cite

show abstract

Excellent 22FDX Hot-Carrier Reliability for PA Applications

Cited by 29 publications

References 4 publications

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-V_p-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-V_p-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

Wide band linearization techniques for RF receiver front-ends

Contact Info

Product

Resources

About

Excellent 22FDX Hot-Carrier Reliability for PA Applications

Cited by 29 publications

References 4 publications

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-Vp-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-Vp-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

Wide band linearization techniques for RF receiver front-ends

Contact Info

Product

Resources

About

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-V_p-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-V_p-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications