Excellent Mechanical Durability of In‐Folding Stress of Poly‐Si Thin‐Film Transistor on Plastic Substrate Compared with Out‐Folding: Generation of Gate Leakage Currents in Flexible Poly‐Si Thin‐Film Transistor by Out‐Folding and Bias‐Temperature Stress

Abstract

The effect of electro‐thermal stress on the electrical performance of flexible, low‐temperature polysilicon (LTPS) thin‐film transistors (TFTs) after mechanical‐folding stress aiming to improve the reliability of foldable display backplanes is studied (IG). Herein, for the first time, the significant increase of gate leakage currents upon the negative bias temperature stress (NBTS) or positive bias temperature stress (PBTS) after the out‐folding test on excimer laser annealing (ELA) TFTs is reported. Out‐folding stress increases the drain current, shifts the threshold voltage (ΔVTH) by 2.4 V, and increases the subthreshold swing without affecting the (IG). However, the ΔVTH is 1.8 V upon NBTS, and the negative ΔVTH is −4.7 V upon PBTS after out‐folding stress along with a drastic increase in IG. A thermal annealing at 250 °C for 10 h for the electro‐thermal stressed TFTs after out‐folding is performed, and initial electrical characteristics recovery is achieved; except the abruptly increased IG. These results are correlated with charge trapping at the damaged grain boundary and (GI). A model with moisture/water molecule diffusion through the nanocracks generated by out‐folding is proposed. The ionized charges (H+, OH−) captured at the nanocrack‐induced trap sites in poly‐Si and GI appear to be the origin of abnormal ΔVTH and IG.

Poly‐Si Thin‐Film Transistors on Polyimide Substrate for 1 mm Diameter Rollable Active‐Matrix Organic Light‐Emitting Diode Display

“…The CNT/ GO mixed layer was formed on carrier glass by spray coating for mechanical detach. [18,19,[34][35][36] The PI was spin-coated to the thickness of 10 μm and then cured at %470 C for 2 h. After forming PI film on CNT/GO backbone on the carrier glass, a multilayer stack (five layers) of silicon dioxide (SiO 2 ) and silicon nitride (SiN x ), 25 nm each, was formed with 125 nm total thickness as a gas barrier by PECVD at 380 C. [19,34,35] A 400 nm-thick SiO 2 buffer layer was deposited on the gas barrier by PECVD at 380 C. Then, a 50 nm-thick hydrogenated amorphous-Si (a-Si:H) film was deposited by PECVD at 360 C and dehydrogenation was carried out in the furnace at 450 C for 2 h. The a-Si was crystallized to poly-Si by excimer laser annealing (ELA) using 308 nm UV laser. Then, a 100 nm SiO 2 was deposited as a GI by PECVD at 380 C and a 200 nm molybdenum (Mo) layer was deposited by sputtering as a gate metal.…”

“…[14] The effects of mechanical strain and electrical reliability of LTPS TFTs have been previously reported (show in Table 1) with the conclusion that the mechanical stability is inferior to oxide TFTs. [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] Therefore, finding a solution to overcome the performance degradation during mechanical stress is important for more flexible and foldable AMOLED displays.In this article, to improve the reliability under mechanical stress, flexible LTPS TFTs were fabricated using three kinds of interlayers (ITLs): inorganic (SiO 2 /SiN x ), hybrid (SiN x /PI), and organic (PI) layers. Reliability test of the LTPS TFTs is performed using bending and rolling machines until 10 000 cycles.…”

“…[14] The effects of mechanical strain and electrical reliability of LTPS TFTs have been previously reported (show in Table 1) with the conclusion that the mechanical stability is inferior to oxide TFTs. [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] Therefore, finding a solution to overcome the performance degradation during mechanical stress is important for more flexible and foldable AMOLED displays.…”

Extremely foldable LTPS TFT backplane using blue laser annealing for low‐cost manufacturing of rollable and foldable AMOLED display

“…First, a solution-processed carbon-nanotube (CNT): graphene-oxide (GO) mixed layer is spray-coated on carrier glass and cured at 290 C. Transparency of the fabricated CNT:GO backbone film is around 90% as shown in Figure 1B. Then, PI solution is spin-coated to a thickness of $10 μm, followed by curing at $470 C for 2 h. The CNT:GO layer reduces the adhesion of the PI on glass and thus can be used as a buffer for mechanical detachment, [13][14][15][16] which is shown in Figure 1A (iii). After the formation of PI substrate, a gas barrier consisting of SiO 2 /SiN x multilayer is deposited through plasma-enhanced chemical vapor deposition (PECVD).…”

3‐1: Distinguished Paper: Foldable LTPS TFT Backplane using Blue Laser Annealing

“…Then, PI solution is spin-coated to a thickness of ~10 μm, followed by curing at ~ 470 o C for 2h. The CNT:GO layer reduces the adhesion of the PI on glass and thus can be used as a buffer for mechanical detachment [13][14][15][16], which is shown in Fig. 1(a(ⅲ)).…”