Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI

Abstract

Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCut TM technology which already allows achieving a maximum total SOI layer thickness variation of less than  10 Å on preproduction volume. Total thickness variation of  5 Å is targeted. SUBSTRATE REQUIREMENT FOR NEXT TECHNOLOGY NODESFor the future 20nm node, standard bulk CMOS technology is facing critical tradeoffs due to increasing random dopant fluctuation, i.e. increasing threshold voltage V T statistical variability. There is consensus in the IC industry that fully depleted (FD) devices with undoped channel, also known as Ultra Thin Body (UTB) devices [1], are effective solution for eliminating random dopant fluctuation (RDF) in the MOSFET channel, thus significantly reducing threshold voltage V T variability by over 60% [2].The foundation of the FD technology is the Ultra Thin SOI (UTSOI) substrate. The starting ultra thin Si thickness (UTSOI) has to be matched to the subsequent FD CMOS processing. Clean, oxidation and etch remove few Si monolayers and it has to be taken into account when specifying the initial UTSOI thickness. The targeted channel Si thickness is typically between 6nm -7nm for 25nm gate length transistor [2]. The starting UTSOI wafers exhibit SOI layer down to 10 nm and buried oxide layer from 145nm down to 10 nm.For FD devices the total random V T variability is the result of gate line edge roughness (LER), workfunction variability and of the channel Si thickness. Since the channel is undoped, there is no significant RDF contribution to V T variability.Thus, the thickness uniformity is a key parameter to avoid additional V T variation of the planar FDSOI device. Typical uniformity requirements include on-wafer uniformity and wafer-towafer uniformity. Both of them combined are classified as layer total thickness variation (LTTV) and define the overall manufacturing process window for thickness uniformity. LTTV has to be achieved at the sub-nanometer range for the UTSOI layer for all wafers and all sites in order to meet the FD specifications. UTSOI substrates target high volume production by second half of 2011 to enable the readiness of a 20nm FD CMOS technology platform. THICKNESS CONTROL REQUIREMENTKakhifirooz et al, have shown an empirical correspondence between V T variation on FD-SOI devices and SOI layer thickness variations. [3,4] From circuit and device considerations the maximum T Si fluctuation that can be tolerated is < 1nm within-wafer (WiW), total wafer range of the T Si non uniformity, and wafer-to-wafer (WtW), T Si reproducibility. This translates in a SOI T Si thickness maximum wafer-to-wafer variation of 5 Å.

Epitaxial Oxides on Glass: A Platform for Integrated Oxide Devices

“…Sample fabrication begins with an ultrathin body SOI wafer (Figure a). Ultrathin body SOI can be fabricated through a variety of processes, including nanocleaving and Soitech’s Smart-Cut technology, , and has already found use in a multitude of devices, including fully depleted field-effect transistors and photonic sensors . The ultrathin body SOI wafers used in this work were provided by Soitech and feature a 45 Å-thick device silicon layer atop a 650 Å-thick buried oxide (BOX) SiO 2 layer.…”

Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

“…45 Present day SOI wafer manufacturing technologies already demonstrate the route to an excellent control of T Si within this desired range. 46 Still, it should be kept in mind that the SOI wafer is subsequently thinned during the device processing steps, to obtain the target sub-10 nm body thickness. This may, in principle, change the T Sifl uctuation patterns and their correlation, introducing a statistical component on a smaller length scale, leading to enhanced statistical variability in devices.…”

Fully depleted SOI (FDSOI) technology

“…The V T sensitivity drops to about 9 mV/nm for long channel transistors. All major SOI substrate suppliers (Soitec, SEH, and SunEdison) have announced the capability of providing 300 mm FDSOI wafers [21,[73][74][75] with wafer-to-wafer and within wafer SOI thickness variation less than ±5Å, meeting the FDSOI substrate requirement [21]. When back bias is used, it is equally important to control the uniformity of the buried oxide (BOX).…”

“…FDSOI has been extensively studied and it is impossible to include all references in this paper. Besides FDSOI, other terminologies used in the literature to depict FDSOI include ultrathin body (UTB) [7-9], ultra-thin body and BOX (UTBB or UT2B) [13][14][15][16], silicon on thin BOX (SOTB) [17,18], ultra-thin SOI (UTSOI) [19][20][21][22], extremely thin SOI (ETSOI) [27][28][29][30][31][32][33][34], and depleted substrate transistor (DST) [35]. In textbook FDSOI transistor is defined as a transistor with a fully depleted channel in contrast to partially depleted SOI (PDSOI).…”