Executable Protocol Specification in ESL

Clarke, Edmund M.; German, Steven M.; Lu, Yuanxu; Veith, Helmut; Wang, Dong

doi:10.1007/3-540-40922-x_13

Cited by 18 publications

(7 citation statements)

References 18 publications

(19 reference statements)

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“…A second direction is to find additional uses for monitor specifications, to maximize their value. One possibility would be interface synthesis for which work has been started by Clarke, Lu, Veith, Wang, and German [12]. A more modest goal would be to extract don't cares from the specification to aid in optimizing a synthesizable description of an interface implementation.…”

Section: Resultsmentioning

confidence: 99%

Monitor-Based Formal Specification of PCI

Shimizu

Dill

2000

Formal Methods in Computer-Aided Design

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Abstract. Bus protocols are hard to specify correctly, and yet it is often critical and highly beneficial that their specifications are correct, complete, and unambiguous. The informal specifications currently in use are not adequate because they are difficult to read and write, and cannot be functionally verified by automated tools. Formal specifications, promise to eliminate these problems, but in practice, the difficulty of writing them limits their widespread acceptance. This paper presents a new style of specification based on writing the interface specification as a formal monitor, which enables the formal specification to be simple to write, and even allows the description to be written in existing HDLs. Despite the simplicity, monitor specifications can be used to specify industry-grade protocols. Furthermore, they can be checked automatically for internal consistency using standard model checker tools, without any protocol implementations. They can be used without modification for several other purposes, such as formal verification and system simulation of implementations. Additionally, it is proved that specifications written in this style are receptive, guaranteeing that implementations are possible. The effectiveness of the monitor specification is demonstrated by formally specifying a large subset of the PCI 2.2 standard and finding several bugs in the standard.

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Section: Resultsmentioning

confidence: 99%

Monitor-Based Formal Specification of PCI

Shimizu

Dill

2000

Formal Methods in Computer-Aided Design

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“…The logic most similar to ours is the one presented in [4]. There a logic for formal specification of hardware protocols is presented, and an algorithm for the synthesis of a Mealy machine is given.…”

Section: Related Workmentioning

confidence: 99%

“…However, Mealy machines are typically "defined" in a natural language such as English. This obviously leads to ambiguities, inconsistencies and plain errors [4].…”

Section: A Mealy Machine (S F ) Consists Of a Set S Of States And Amentioning

confidence: 99%

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Coalgebraic Logic and Synthesis of Mealy Machines

Bonsangue

Rütten

Silva

2008

Foundations of Software Science and Computational Structures

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Abstract. We present a novel coalgebraic logic for deterministic Mealy machines that is sound, complete and expressive w.r.t. bisimulation. Every finite Mealy machine corresponds to a finite formula in the language. For the converse, we give a compositional synthesis algorithm which transforms every formula into a finite Mealy machine whose behaviour is exactly the set of causal functions satisfying the formula.

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“…Brand [19] proposed exploiting information from the design specification to significantly reduce the complexity of simulation. Clarke et al further researched the problem of specifications and generators in [20]. However, BDDs were used to demonstrate a practical approach to this problem in the SimGen project [21].…”

Section: Previous Workmentioning

confidence: 99%

Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands

Shekhar

Kalla

Meredith

et al. 2006

2006 Formal Methods in Computer Aided Design

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Abstract-This paper addresses simulation-based verification of highlevel descriptions of arithmetic datapaths. Instances of such designs are commonly found in DSP for audio, video and multimedia applications, where the word-lengths of input/output bit-vectors are fixed according to the desired precision. Initial descriptions of such systems are usually specified as Matlab/C code. These are then automatically translated into behavioural/RTL descriptions (HDL) for subsequent hardware synthesis.In order to verify that the initial Matlab/C model is bit-true equivalent to the translated RTL, how many simulation vectors need to be applied? This paper explores results from number theory and commutative algebra to show that exhaustive simulation is not necessary for testing their equivalence. In particular, we derive an upper bound on the number of simulation vectors required to prove equivalence or identify bugs. These vectors cannot be arbitrarily generated; we determine exactly those vectors that need to be simulated. Extensive experiments are performed within practical CAD settings to demonstrate the validity and applicability of these results.

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Executable Protocol Specification in ESL

Cited by 18 publications

References 18 publications

Monitor-Based Formal Specification of PCI

Monitor-Based Formal Specification of PCI

Coalgebraic Logic and Synthesis of Mealy Machines

Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands

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