Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration

Hanna, Darrin M.; DuChene, Michael

doi:10.1016/j.micpro.2006.10.001

Cited by 3 publications

(3 citation statements)

References 18 publications

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“…The number of I/O must also be considered. In fact, a similar architecture exists that uses only 2 FPGAs [5]. This is an advantage of flowpaths over using other methods, such as Handel-C, for generating hardware from software.…”

Section: Resultsmentioning

confidence: 99%

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Speedup using Flowpaths for a Finite Difference Solution of a 3D Parabolic PDE

Hanna

Spagnuolo

DuChene

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Partial differential equations (PDEs) are used to model physical phenomena and then appropriate convergent numerical algorithms are employed to solve them and create computer simulations.In many important applications, such as weather prediction and contaminant transport processes, simulation outputs are required in real time or even faster, yet the spatial component of the problem is very large, thereby increasing the computational time. In addition, often times numerical scientists work in groups to create a large-scale code, but they work individually on PCs to test components of the code, so that speedup of the computational algorithms on PCs is desirable. There is a benefit to creating and using custom hardware to perform the numerical calculations faster than commodity hardware.This work uses a high-level programming language (Java) to behaviorally describe, and then implement, a finite difference solution of a parabolic PDE as a custom hardware circuit targeted to an FPGA. The results show that the circuits can perform the calculations 1 to 2 orders of magnitude faster than commodity hardware.

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Section: Resultsmentioning

confidence: 99%

“…Flowpaths can outperform microprocessors at lower clock frequencies and therefore consume less power than microprocessors or microprocessor cores. Flowpaths can be partitioned into subsets that can take advantage of runtime dynamic partial reconfiguration [5].…”

Section: Flowpathsmentioning

confidence: 99%

Speedup using Flowpaths for a Finite Difference Solution of a 3D Parabolic PDE

Hanna

Spagnuolo

DuChene

2007

2007 IEEE International Parallel and Distributed Processing Symposium

Self Cite

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“…G. Seth Copen et al designed PipeRench [5] to overcome the disadvantages of using FPGA as reconfigurable computing fabrics through the hardware virtualization. M. H. Darrin and D. Michael proposed Flowpaths [6] through using lowcapacity FPGA to execute large circuit. This approach allowed one FPGA executing while another low-capacity FPGA was being dynamically reconfigured.…”

Section: Related Workmentioning

confidence: 99%

Homogeneous NoC-based FPGA: The Foundation for Virtual FPGA

Yang

Yan

et al. 2010

2010 10th IEEE International Conference on Computer and Information Technology

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Reconfigurable computing based on FPGAs (Field Programmable Gate Arrays) has been a promising solution to improve the performance with high flexibility. However, the physical capacity limitation of FPGAs prevents its wide adoption in real world. In this paper, a homogeneous NoCbased FPGA architecture is proposed, in which reconfigurable and I/O resources are interconnected via NoC so that reconfigurable modules can be placed anywhere once enough space available. Meanwhile, a virtual FPGA is proposed with which over large circuit can be implemented on a limited capacity FPGA. The experiment verified that our approach can provide more flexible reconfiguration, and combing NOC on FPGA, the resource utilization increased within 44.7%-53.5% because of the fragment in CRs benefit from such kind of dynamic partial configuration.

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Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays

Lê

Fung

Tam

et al. 2014

International Journal of Information Technology Project Management

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Genetic algorithms (GAs) have found many applications in various fields such as physics, signal processing, artificial intelligence and recently construction engineering management. For a long time, GAs are usually criticized to be time-consuming, making it unpractical for real-time applications. This paper presents a new technique which can be used: (1) to automate construction activities, and (2) to improve building information modeling which has become an attractive research topic around the world. Different from the generic GA techniques employed in the literature, this paper proposes a new GA using hardware with field-programmable gate arrays. The proposed technique is shown to improve speed and lessen computational power. Hardware implementation of GA using static random access memory-based field-programmable gate arrays with synthesizable very hardware description language coding is introduced. Detailed analyses on the field-programmable gate arrays are given which show that it is suitable for real-time applications. As a result, GA is modified so that it can be implemented in series and parallel which can greatly improve computational hardware performance. Configuration of parallelization is available with a peripheral component interconnect interface, which further helps to form a fast optimization tool for real-time applications. The ultimate goal of this paper is thus to design an effective GA technique which can be employed to support building information modeling and to effectively automate critical processes in construction projects.

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Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration

Cited by 3 publications

References 18 publications

Speedup using Flowpaths for a Finite Difference Solution of a 3D Parabolic PDE

Speedup using Flowpaths for a Finite Difference Solution of a 3D Parabolic PDE

Homogeneous NoC-based FPGA: The Foundation for Virtual FPGA

Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays

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