Execution Architecture: The DELtran Experiment

Flynn,; Hoevel,

doi:10.1109/tc.1983.1676200

Cited by 26 publications

(8 citation statements)

References 9 publications

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“…The results suggest that if a separate cache is used to hold the local variables, it need not be large to obtain a high hit rate. In fact, this has been the motivation for some previous work [8,12,26,29].…”

Section: Introductionmentioning

confidence: 95%

“…To service local variable accesses efficiently, a specialized hardware organization to simulate the run-time stack may appear attractive [8,12,26]. However, we use a more general cache design called the local variable cache (LVC) in the framework of our data-decoupled architecture.…”

Section: Architectural Supportmentioning

confidence: 99%

“…The stack cache is effectively a large register file to simulate the run-time stack that replaces the general register file. The contour buffer proposed by Flynn and Hoevel [12] in their Directly Executed Languages model, is a programmeraddressable buffer that is used in conjunction with the run-time stack in memory. Stanley and Wedig [26] proposed three buffer management algorithms for a Top of Stack (TOS) buffer, which is a register file designed to cache the top elements of the stack.…”

Section: Related Workmentioning

confidence: 99%

“…To service the local variable accesses efficiently, we study two optimizations -fast data forwarding and access combining. Although there have been efforts to optimize local variable accesses with hardware support in the past [8,12,26], little work has been done to study their performance impact in the context of a wideissue superscalar processor with a multi-ported data cache. Experimental results based on an execution-driven simulator and a set of SPEC95 integer and floating-point programs suggest that the proposed approach can achieve comparable or better performance than a conventional approach.…”

Section: Introductionmentioning

confidence: 99%

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Decoupling local variable accesses in a wide-issue superscalar processor

ChoSangyeun¹,

YewPen-Chung²,

LeeGyungho³

1999

SIGARCH Comput. Archit. News

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Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data cache, however, becomes increasingly inefficient and can add to the hardware complexity significantly. This paper takes an alternative or complementary approach for providing more data bandwidth, called the data-decoupled architecture. The approach, with support from the compiler and/or hardware, partitions the memory stream into two independent streams early in the processor pipeline, and feeds each stream to a separate memory access queue and cache. Under this model, the paper studies the potential of decoupling memory accesses to program's local variables that are allocated on the run-time stack. Using a set of integer and floating-point programs from the SPEC95 benchmark suite, it is shown that local variable accesses constitute a large portion of all the memory references, while their reference space is very small, averaging around 7 words per (static) procedure. To service local variable accesses quickly, two optimizations, fast data forwarding and access combining, are proposed and studied. Some of the important design parameters, such as the cache size, the number of cache ports, and the degree of access combining, are studied based on simulations. The potential performance of the proposed scheme is measured using various configurations, and it is concluded that the scheme can become a viable alternative to building a single multi-ported data cache.

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Section: Introductionmentioning

confidence: 95%

Section: Architectural Supportmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Decoupling local variable accesses in a wide-issue superscalar processor

ChoSangyeun¹,

YewPen-Chung²,

LeeGyungho³

1999

SIGARCH Comput. Archit. News

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“…Several good surveys on this topic are available in the literature [1,7]. The research approaches are very different [1,9,10,11,12,14]. In all these approaches, however, the basic problem is how to bridge efficiently the semantic gap that exists between the HLL architecture and the processor architecture.…”

Section: Introductionmentioning

confidence: 99%

Mapping HLL constructs into microcode for improved execution speed

Milutinović¹,

Roberts²,

Hwang³

1984

SIGMICRO Newsl.

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A processor architecture is presented which enables the constructs typical of HLLs to be mapped into the constructs typical of microcode. This mapping is provided only for selected HLL primitives and HLL statements with a relatively small number of operands and parameters • We are concerned about the optimal hardware/software trade-off, and not about the absolute 1:1 correspondence between HLL statements and highly horizontal microcode. Still, our approach enables the software for time-critical applications to be entirely written in the HLL and executed in the microcode, without the execution-time deteriorations typical for the systems with a large semantic gap between the HLL architecture and the processor architecture. This approach is particularly suitable for the time-critical dedicated control and signal processing. Using an extended subset of Fortran 77, one that matches the typical demands of the specified application area, it is shown that the proposed architecture supports the mapping of HLL constructs into microinstructions. A flexible register-transfer level simulator has been designed and implemented. It was used to run kernel routines on various configurations of the proposed architecture.

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Attributed linear intermediate representations for retargetable code generators

Ganapathi

Fischer

1984

Softw Pract Exp

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This paper illustrates the usefulness of an attributed prefix linear intermediate representation for compiler code generation. In separating the machine‐independent and machine‐dependent aspects of a compiler, we discuss the advantages and disadvantages of an attributed linear intermediate representation with respect to tree‐structured intermediate representations. Some of these issues are relevant to fundamental questions of compiler structure with particular emphasis on retargetability. We discuss our implementation experience using this linear intermediate representation with a table‐driven code generation scheme for a variety of target architectures.

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Execution Architecture: The DELtran Experiment

Cited by 26 publications

References 9 publications

Decoupling local variable accesses in a wide-issue superscalar processor

Decoupling local variable accesses in a wide-issue superscalar processor

Mapping HLL constructs into microcode for improved execution speed

Attributed linear intermediate representations for retargetable code generators

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