Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms

Abstract

In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardware models written in VHDL. We survey central event queue, conservative distributed and optimistic distributed PDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of these algorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at the University of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. We present measurements taken from this kernel simulating some benchmark models. It appears that this technique, which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktop multiprocessor workstations), simulating behavioral and register transfer level models. However, the degree of useful parallelism achievable on gate level models with this technique appears to be limited.

Distribución de carga y aumento del grado de paralelismo en simulación síncrona de lenguajes de descripción hardware

“…No hay muchos simuladores paralelos síncronos de VHDL con los que comparar este algoritmo, pero aún así nos fijaremos en dos bastante conocidos. Uno es el realizado en la Universidad de Adelaide por Ashenden ([Ashenden93], [Ashenden94a], [Ashenden94b]). Este simulador tiene un núcleo monolítico y una cola de eventos centralizada.…”