Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors

Pothineni, Nagaraju; Kumar, Anshul; Paul, Kolin

doi:10.1109/vlsi.2008.93

Cited by 13 publications

(8 citation statements)

References 17 publications

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“…Apart from this, there are some techniques/ algorithms proposed by some researchers that only focused convex maximal subgraph for the same purpose. An algorithm used in [11] accelerates the entire design space optimally by considering all legal patterns of subgraph which satisfies few architectural constraints. Similarly an approach [12] also generates custom instructions without imposing any restrictions on the number of input and output operands on enumerated convex subgraph.…”

Section: Fig 3: Synthesis Of the Customized Hardware And Software Commentioning

confidence: 99%

Instruction Customization: A Challenge in ASIP Realization

Shrimal¹,

Jain²

2014

IJCA

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An Application Specific Instruction set Processors (ASIP) or alternatively known as customized processor is a processor designed for a particular application or for a set of applications. Earlier surveys show that though a significant research has been done for this most promising processor design technology, still approaches used in them are lacking in methodologies to define processor configuration based on the requirements of the applications. There are number of approaches claiming to design and synthesize ASIPs but they are facing many challenges. This paper is an attempt to find major challenges faced by them as well as the current state of these promising techniques adopted by the industry. This paper also analyzed their effort to know really what they could have achieved so far and identified what should be done to make these techniques successful. If some limitations can be removed soon, these techniques are going to expand in an explosive manner.

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Section: Fig 3: Synthesis Of the Customized Hardware And Software Commentioning

confidence: 99%

Instruction Customization: A Challenge in ASIP Realization

Shrimal¹,

Jain²

2014

IJCA

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“…In [17] the authors provided a new algorithm for faster enumeration of legal patterns. They proposed an iterative process which reduced their algorithm runtime by up to two orders of magnitude when compared to the existing work.…”

Section: Pattern Identificationmentioning

confidence: 99%

FPGA-aware techniques for rapid generation of profitable custom instructions

Prakash¹,

Lam²,

Clarke

et al. 2013

Microprocessors and Microsystems

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Instruction set extension of FPGA based reconfigurable processors provides an effective means to meet the increasingly strict design constraints of embedded systems. We have shown in our previous works [20][21] that the usage of FPGA architectural constraints for pruning the design space during enumeration of custom instructions/patterns not only leads to notable reduction in the time taken to identify custom instructions but can also result in the selection of profitable custom instructions when the area is highly constrained. However when area constraint is relaxed, the previously proposed methods failed to perform better than traditional methods. In this paper, we propose a heuristic to identify profitable custom instructions for designs with arbitrary area constraints. The proposed heuristic relies on a new pruning criterion to enumerate patterns with high size-tohardware-area ratio. We also proposed a suitable algorithm to select profitable custom instructions from the enumerated patterns. The proposed template selection algorithm takes advantage of the FPGA area-time measures of the enumerated patterns, which can be easily inferred from the FPGA-aware enumeration strategy. Experimental results show that the proposed methods in this paper result in custom instructions that achieve an average performance gain of 76.23 % over current state-of-the-art approaches.

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“…Step 2 enumerates the convex subgraphs of each input ISE and partitions them into isomorphic equivalence classes (IECs) as described by Pothineni et al [13]. For every pair of vertex u and v in convex subgraph S, every path from u to v or from v to u contains only vertices in S. A mergeable class (MC) is an IEC that contains at most one subgraph per ISE.…”

Section: Heuristicmentioning

confidence: 99%

“…Extensible processors allow the user to augment a base processor, typically an in-order RISC or VLIW, with application specific custom instruction set extensions (ISEs) [4,[13][14][15]17]. ISEs may be realized in ASIC technology, along with the processor, or synthesized on a closely-coupled reconfigurable datapath.…”

Section: Introductionmentioning

confidence: 99%

A high-level synthesis flow for custom instruction set extensions for application-specific processors

Pothineni¹,

Brisk

Ienne

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize a new technique for resource allocation, binding, and port assignment during synthesis. Our method is derived from prior work on datapath merging, and increases area reduction by accounting for the cost of multiplexors that must be inserted into the resulting datapath to achieve multi-operational functionality.

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Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors

Cited by 13 publications

References 17 publications

Instruction Customization: A Challenge in ASIP Realization

Instruction Customization: A Challenge in ASIP Realization

FPGA-aware techniques for rapid generation of profitable custom instructions

A high-level synthesis flow for custom instruction set extensions for application-specific processors

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