Expedited EM‐driven generation of Pareto‐optimal trade‐off curves for variable‐turn on‐chip inductors

Abstract

This work presents a novel approach to computationally efficient Pareto front identification for variable‐turn on‐chip inductors. The final outcome is a set of solutions that correspond to the best trade‐offs between conflicting design objectives. Here, we consider minimising inductor area and, simultaneously, maximising its quality factor, while maintaining a specified inductance value at a given operating frequency. As opposed to the typically used population‐based metaheuristics requiring massive computational resources to generate the entire Pareto front in a single algorithm run, the proposed method reduces the number of necessary structure evaluations by exploiting a point‐by‐point strategy for determining the consecutive trade‐off designs. The original design problem is a mixed‐integer task involving integer and non‐integer variables (here, the number of inductor windings and its geometry parameters). For the sake of computational efficiency, we develop a separate kriging interpolation model for each considered case of winding turns, and use it, instead of expensive electromagnetic simulations, to obtain the initial Pareto fronts. The non‐dominated part of the concatenated initial Pareto sets is subsequently elevated (accuracy‐wise) to the level of an electromagnetic analysis by means of a response correction technique. Our considerations are illustrated using a 3.5‐nH variable‐turn on‐chip inductor realised in 65‐nm CMOS technology.

Machine Learning-Based Modeling and Generic Design Optimization Methodology for Radio-Frequency Microelectromechanical Devices

“…Alternatively, machine learning techniques can be used to map the FEM simulation data over the desired design space, into intelligent yet computationally cheap surrogate models capable of performing accurate predictions during optimization iterations. This technique, although less accurate, can drag down the computational costs into reasonable limits [11,12].…”

“…Therefore, in order to alleviate these design challenges, a more advanced optimization approach must be followed. Although formal design optimization techniques exist and are quite common in the design of RFIC components [11][12][13][14] or typical MEMS devices [15,16], such approaches have been overlooked for RF-MEMS devices which combine the two domains. For instance, an earlier work utilized metaheuristic optimization techniques in order to obtain optimal sets of design variables for planar CMOS RF inductors [13].…”