Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC

Abstract

a b s t r a c t 3D technologies are investigated for the upgrade of the ATLAS pixel detector at the HL-LHC. R&D focuses on both, IC design in 3D, as well as on post-processing 3D technologies such as Through Silicon Via (TSV). The first one uses a so-called via first technology, featuring the insertion of small aspect ratio TSV at the pixel level. As discussed in the paper, this technology can still present technical challenges for the industrial partners. The second one consists of etching the TSV via last. This technology is investigated to enable 4-side abuttable module concepts, using today's pixel detector technology. Both approaches are presented in this paper and results from first available prototypes are discussed.

Test results of the first 3D-IC prototype chip developed in the framework of HL-LHC/ATLAS hybrid pixel upgrade

“…The test has demonstrated a very good communication between tiers, having all pixels connected 2014 JINST 9 C02031 for some ICs, despite an overall very bad chip yield on the wafer. This is demonstrated in figure 2, where the reader can observe identical maps recorded either directly in the analogue tier or through the BIs and TSVs in the digital tier [9].…”

The path towards the application of new microelectronic technologies in the AIDA community

“…Interconnection bonds between layers have a 4 µm pitch. CMOS pixel sensors and two-layer integrated circuits have been fabricated and successfully tested in this Tezzaron technology by Fermilab which organized the first MPW run [14] and by research groups in AIDA WP3 [15,16], providing an extensive demonstration of the potential of high-density 3D processes. In WP3, on the basis of these results, there are plans for submitting new 3D chips with the Tezzaron process, and design studies were already carried out to define the circuit architecture and the pixel layout in these new devices.…”