Experience with Applying Formal Methods to Protocol Specification and System Architecture

Azimi, Mani; Chou, Ching-Tsun; Kumar, Akhilesh; Lee, Victor W.; Mannava, Phanindra K.; Park, Seungjoon

doi:10.1023/a:1022965204416

Cited by 4 publications

(3 citation statements)

References 9 publications

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“…A research group, with extensive protocol verification experience, was using the Murφ verification system to model and verify one proposal [1]. Another development team, with significant experience developing protocols, was using TLA+ to create and model a new protocol proposal and verifying it with TLC [2].…”

Section: Protocol Fvmentioning

confidence: 99%

Pre-RTL formal verification

Beers

2008

Proceedings of the 45th Annual Design Automation Conference

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During the recent development of a next-generation Intel processor, the project's formal verification team verified a new coherence protocol and portions of its RTL implementation against the protocol's specification within project deadlines. Typically, FV teams apply formal property verification (FPV) after RTL is coded and, though it continues to be an effective complement to pre-silicon validation, this late application prevents it from keeping pace with the continual complexity increases in hardware designs. Our discussion centers around how applying FV early in the development cycle of this processor enabled continual verification as the design progressed, culminating with the targeted RTL verification. We also present the languages and methodologies used, the reasons behind the choices, and where improvements can be made.

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Section: Protocol Fvmentioning

confidence: 99%

Pre-RTL formal verification

Beers

2008

Proceedings of the 45th Annual Design Automation Conference

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“…[4], [8], [3], [13]). The HLM is a simplified version of the component that still models key functionality.…”

Section: Introductionmentioning

confidence: 99%

Industrial strength refinement checking

Bingham

Erickson

Singh

et al. 2009

2009 Formal Methods in Computer-Aided Design

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Abstract-This paper discusses a methodology used on an industrial hardware development project to validate various cache-coherence protocol components. The idea is to use a high level model (HLM) written in Murphi for model checking purposes, and then to use the HLM as a checker during dynamic (i.e. simulation based-) validation of the RTL. Such a checker requires a formal notion of what it means for the RTL to implement the HLM. Due to RTL pipelining, concurrency, and different RTL/HLM semantics, an appropriate notion is nonobvious. We employ a notion we call behavioral refinement, and describe a methodology for creating refinement checkers. A novel aspect of our methodology is that all "ingredients" are specified using System Verilog (SV): even the Murphi model itself is compiled into SV. Thus any off-the-shelf SV simulation engine can be used. We report the successful use of our refinement checkers to catch bugs in a real project at Intel and give an example illustrating our methodology.

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“…We have applied this approach to a cache coherence protocol that is unusual (caches are maintained on doubly-linked lists) and complex (37 cache states) called SIMPL. We are not the first to do table-based design [1,2,4], but it is one thing to ask designers to write tables in a style intended for formal analysis, and it is another to take tables as they are written by the designers and make formal sense of them. We require no language or GUI for building the model, and impose no rigid philosophy on how protocols should be described.…”

mentioning

confidence: 99%

Extracting models from design documents with mapster

James

Leonard

O’Leary

et al. 2008

Proceedings of the Twenty-Seventh ACM Symposium on Principles of Distributed Computing

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We cannot apply PODC methodologies to industrial designs without formal models of the designs. Formal models are usually hard to find. We have built a tool that extracts formal models directly from design documents. Protocol verification consists of three easy steps: find a protocol, model the protocol, and verify the protocol. Go ahead, laugh at the joke, but it is not much of an exaggeration to say that getting the protocol model has traditionally been the hardest of the three steps at companies like Digital, Compaq, HP, and Intel. We could talk for an hour on the reasons, but the bottom line is that the tools we build assume the existence of a model, and we think very little about where these models come from, yet our tools will never gain widespread use if we don't address the problem of building the model of an industrial design.Industry often uses the "Superman approach" to model building. (Superman is a fictional comic book superhero once popular in America.) In this approach, a single verification expert joins a group (usually late), spends months learning the protocol, building a model, changing the model as the design changes, and only then gets to do any verification. This is not the right approach. For one thing, it doesn't scale well (there aren't many supermen), it burns out the supermen we have (leaving even fewer supermen), and it never gets past the "technology demonstration" phase ("That was great, Superman, you wanna do it for me again?").While not building models, designers are producing a number of design artifacts with significant technical content: microarchitecture specification documents containing state transition tables, block diagrams, pipeline diagrams, timing diagrams, message flows, etc. We should be able to use this information to build the formal model we need from what the designers are already willing to produce. And once the model is built, it could be highly attractive to the designers to include it in their documents, leading to more precise, less ambiguous design documents. This is our dream:• A front-end that can extract from a specification document the transition tables, block diagrams, pipeline diagrams, etc, and build a formal protocol model.• A back-end that can take this protocol model and produce input to formal verification tools, and produce reference models for traditional simulation.What we have done is build a tool that mechanically extracts tabular information from a design document -state transition tables, state definitions, type definitions, etc -and builds a mathematical protocol model, and from that model generates a Murphi model [3] for model checking. We have applied this approach to a cache coherence protocol that is unusual (caches are maintained on doubly-linked lists) and complex (37 cache states) called SIMPL. We are not the first to do table-based design [1, 2, 4], but it is one thing to ask designers to write tables in a style intended for formal analysis, and it is another to take tables as they are written by the designers and make formal sense ...

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Experience with Applying Formal Methods to Protocol Specification and System Architecture

Cited by 4 publications

References 9 publications

Pre-RTL formal verification

Pre-RTL formal verification

Industrial strength refinement checking

Extracting models from design documents with mapster

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