A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO, films formed over the abrupt topography of fine-line (2.0-pm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO, must be maintained at -0.4 (3800 and 9100 A/min, respectively) with an Ar/CF4/OZ high pressure plasma generated in a low radio-frequency etching system.