Experimental determination of short-channel MOSFET parameters

Chen, Hao; Cabon-Till, B.; Cristoloveanu, S.; Ghibaudo, G.

doi:10.1016/0038-1101(85)90034-6

Cited by 50 publications

(5 citation statements)

References 9 publications

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“…In Figure 10, we compared for both the devices, the measured taken at different gate lengths ( = 6 m, 8 m, and 100 m), and for different positive gate voltages ( GS = 0 V, 1 V, and 4 V). For the UTBs, exhibits a linear growth trend with , and a decreasing trend with GS as expected from the classic MOSFET channel resistance [31,32]. Surprisingly, for NSB devices, is found almost constant with .…”

Section: 1supporting

confidence: 60%

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Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

Karsenty

Chelly

2013

Active and Passive Electronic Components

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Ultrathin body (UTB) and nanoscale body (NSB) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

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Section: 1supporting

confidence: 60%

“…results based on the classic -technique [31,32] and the gate-to-channel capacitance measurement (or "split -" method) [33].…”

Section: Complementary Results For the Elucidation Of Series Resistancementioning

confidence: 99%

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

Karsenty

Chelly

2013

Active and Passive Electronic Components

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“…The platinum silicide film on source/drain areas serves to reduce the total parasitic resistance in series with the channel. A method after Hao et al (22) was adopted to The simulations thus confirm that for these relatively low parasitic resistances, no drastic improvement of device performance is obtained by a further reduction achieved with a silicide layer on source/drain areas. The resistance outside the metallurgical source/drain junctions does not depend on the channel length of the device.…”

Section: Device Characterizationmentioning

confidence: 86%

A Refined Polycide Gate Process with Silicided Diffusions for Submicron MOS Applications

Norström¹,

Nygren²,

Johansson³

et al. 2019

J. Electrochem. Soc.

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A polycide process with silicided diffusions is presented. This allows simultaneous use of mutually different silicides on the gate electrode and on the respective source and drain areas. The novel technique was used to fabricate MOSFETs and TiSi~/poly-Si gate electrodes and self-aligned PtSi on source/drain regions. Respective sheet resistivities were 5 and 7-812/[3 and no degradation effects were observed. A comparison with the more conventional salicide concept is made and several advantages are elucidated.As integrated MOSFET dimensions are reduced, contact and interconnection parasitics tend to become more important and will ultimately limit overall circuit performance. Novel or modified processes have therefore been proposed to overcome or alleviate these effects. In the polycide configuration (1) the polycrystalline silicon on the gate level is shunted by a silicide overlayer in order to reduce RC time constants and IR voltage drops. This layer is normally deposited prior to source/drain formation and must be stable at temperatures around 900~ For this reason, only refractory silicides (e.g., WSi2, MoSi2, TaSi2, or TiSi2) have been seriously considered for this application. A silicide top layer may reduce the sheet resistivity by a factor of 10-20 relative to a single layer of doped polysilicon.More recently, low resistive coatings have also been proposed for the source/drain diffusions, as corresponding sheet resistivities increase due to reduced junction depths. It has been suggested that a shunt layer could reduce the parasitic series resistance and relax the misalignment sensitivity. In the so-called salicide (self-aligned silicide) technique (2) a silicide is formed on exposed silicon regions by direct reaction with a deposited metal. Thus the source/ drain areas and the gate level interconnections are simultaneously silicided without any additional photo masking step. Unreacted metal on oxide-masked regions is subsequently removed in a selective wet etch. Self-aligned formation of platinum silicide is a well-established technique that has been in use for a long time (3). As metal atoms are the dominant diffusing species in the formation of this silicide, very good selectivity with minimal lateral growth can be achieved. For MOS applications according to the salicide concept, the disilicides of titanium (4) and cobalt (5) have been, however, most thoroughly studied.Two major constraints inherent to the sa[icide method are eliminated in the process to be described in this paper:1. The same silicide and the same layer thickness is used on the gate electrode and on the source/drain regions. Consequently, respective metallizations cannot be individually optimized, but a compromise has to be made. * Electrochemical Society Active Member. 1 Present Address: IMEC Laboratory, B-3030 Leuven, Belgium.2. Great care has to be taken to prevent short circuits between the gate electrode and the source/drain regions. As these are separated by dielectric spacers only a few tenths of a micron wide, lateral silicide gro...

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“…Several explanations regarding the mobility degradation behavior in the short-channel regime were proposed in the past, including halo implants and quasi-ballistic transport characteristics performed in these nanoscale devices. 2,12 This issue, nevertheless, deserves further study in the future. Using the extracted eff ͑L TEM ͒ in Eq.…”

Section: H36mentioning

confidence: 94%

Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs

Chen

Goto

et al. 2009

J. Electrochem. Soc.

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This paper presents a BSIM-based method for source/drain series resistance and mobility extraction in nanoscale strained-silicon metal oxide semiconductor field effect transistors ͑MOSFETs͒ with halo implants. This method is more accurate than the conventional channel-resistance and shift and ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally nonuniform channel doping. We have verified this method using samples with different stressor/ doping conditions and good agreement with experimental data has been obtained. The accuracy of the Berkeley Short-channel IGFET model ͑BSIM͒ R sd extraction method is also proven by simulated current-voltage characteristics with different external resistant values. Significant mobility degradation in the short-channel regime has been observed for various uniaxial stressors. This method may serve as a suitable process monitor tool for ultrashallow junction and strained process development.

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Experimental determination of short-channel MOSFET parameters

Cited by 50 publications

References 9 publications

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

A Refined Polycide Gate Process with Silicided Diffusions for Submicron MOS Applications

Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs

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