Experimental Evaluation of Gate Architecture Influence on DG SOI MOSFETs Performance

Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperatures

“…Of the numerous works devoted to their investigation, most are focused on technological approaches to fabricate them [2][3][4][5][6][7][8][9][10], on their immunity to the short channel effects [2,4,[11][12][13][14], on their digital [15][16][17] and analog/RF performances [16,[18][19][20]. However, very few information is available about their behavior at high temperatures.…”

Characteristic Analysis of Dual Gate Metal Oxide Semiconductor Field Effect Transistor by Mathematical Modeling

“…The new methodologies give rise to two paths; one is the introduction of new materials into the classical single gate MOSFETs where we can develop uniaxial/biaxial strain (Widiez et al, 2005;Smith, 2008;Vaddi et al, 2012) and which improves the carrier mobility and drive current by introducing new materials in the channel region. Second is the development of non-classical Multigate MOSFETs which is very good concept for further scaling of the device dimensions (Antoniadis et al, 2006;Keyes, 1986;Dunga et al, 2006).…”

“…Since bulk MOSFETs are expected to reach their limit for gate lengths below 30 nm (Chaudhry and Kumar, 2004;Brown et al, 2002), alternative architectures have been proposed to overcome their limitations. The DoubleGate (DG) transistor is considered one of the most promising devices for extremely scaled CMOS technology generations (Widiez et al, 2005).…”

“…Advantage of Double gate SOI MOSFET over conventional, Single Gate MOSFET can be described in terms of performance and potential for ultimate Scaling. The Peculiarity of DG-MOSFET is that the top and bottom gates are biased simultaneously to established equal surface potential VG1 = VG2, for identical gate oxides, Or VG1 = VG2 (tox1/tox2) to compensate for the difference in front and back oxide thickness (Widiez et al, 2005).…”

Analog performance investigation of misaligned double gate junctionless transistor

“…Wong et al [18] provided the insight into the gate misalignment based on numerical simulation and showed that the subthreshold performance gets degraded due to asymmetry when compared with a symmetric DG MOS device. Widiez et al [19] have shown experimentally that oversized back gate has more tolerance to gate misalignment. Yin et al [20] have reported that misalignment at source side (DG_S) has larger short channel effect (SCE) compared to misalignment at drain side (DG_D).…”