Experimental Insights from the Rogues Gallery

Young, Jeffrey; Riedy, Jason; Conte, Thomas M.; Sarkar, Vivek; Chatarasi, Prasanth; Srikanth, Sriseshan

doi:10.1109/icrc.2019.8914707

Cited by 12 publications

(5 citation statements)

References 33 publications

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“…Tutorials focusing on the GT Emu Chick and Pathfinder systems have been presented at several conferences, either as components of a broader RG tutorial for the ASPLOS19 and PEARC19 conferences [19,20], or as a dedicated presentation for the PEARC21 and HPEC22 conferences [26,27] in an online-only format. Additionally, proposals were submitted to present tutorials at PEARC22 and SC22 but were not selected for the final program.…”

Section: Community Tutorial Experiencesmentioning

confidence: 99%

“…Given the major shift in infrastructure, the need for a well-developed user community and management workforce is readily apparent. The Rogues Gallery is an NSF-funded novel architecture testbed designed to provide early experiences for a variety of resources [28], with training being one of its core tenets. Approaches based on nearmemory computation (of which CXL is a subset), reconfigurable hardware, advanced networking, and neuromorphic processing are hosted, allowing students and researchers to consider how these architectures can be leveraged, either using current software capabilities or through novel algorithm design, to tackle many of the problems in HPC.…”

Section: Introductionmentioning

confidence: 99%

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Multifaceted Approaches for Introducing a Hardware-Thread Migratory Architecture

Jezghani,

Young,

Mallela

et al. 2023

JOCSE

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The challenges of HPC education span a wide array of targeted applications, ranging from developing a new generation of administrators and facilitators to maintain and support cluster resources and their respective user communities, to broadening the impact of HPC workflows by reaching non-traditional disciplines and training researchers in the best-practice tools and approaches when using such systems. Furthermore, standard x86 and GPU architectures are becoming untenable to scale to the needs of computational research, necessitating software and hardware co-development on less-familiar processors. While platforms such as Cerebras and SambaNova have matured to include common frameworks such as TensorFlow and PyTorch as well as robust APIs, and thus are amenable to production use cases and instructional material, other systems may lack such infrastructure maturity, impeding all but the most technically inclined developers from being able to leverage the system.We present here our efforts a nd o utcomes o f p roviding a codevelopment and instructional platform for the Lucata Pathfinder thread-migratory system in the Rogues Gallery at Georgia Tech. Through a collection of user workflow management, co-development with the platform's engineers, community tutorials, undergraduate coursework, and student hires, we have been able to explore multiple facets of HPC education in a unique way that can serve as a viable template for others seeking to develop similar efforts.

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Section: Community Tutorial Experiencesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multifaceted Approaches for Introducing a Hardware-Thread Migratory Architecture

Jezghani,

Young,

Mallela

et al. 2023

JOCSE

View full text Add to dashboard Cite

show abstract

“…Finally, the third contribution [12] presents a testbed [13,14,15,16] covering networking, identity management, resource scheduling and tools along with techniques they have developed to manage these Post-Moore devices. More than a methodology, it presents several methods to evaluate different Post-Moore architectures with different tests.…”

Section: State Of the Artmentioning

confidence: 99%

A Methodology for Evaluating the Energy Efficiency of Post-Moore Architectures

Yepes

Barrios-Hernandez

Steffenel

2022

Communications in Computer and Information Science

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The improvement of computational systems has been based on Moore's law and Dennard's scale, but for more than a decade it has started to fall to a standstill. To maintain the improvement new technologies are proposed, this has established a Post-Moore era. Currently there are different methodologies to evaluate emerging devices and technologies, but the results of these methodologies end up being particular solutions. This paper presents a methodology that can evaluate Post-Moore devices or technologies in an agile way, characterizing an application, choosing a device that meets its needs, selecting tests and parameters that are executed to meet the objectives set by the methodology. The results show how to evaluate the energy efficiency of these new technologies, but the scope of the methodology can cover other needs.

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“…Figure 2 shows the layout of the two clusters that were used in Spring 2022 to support reconfigurable computing and computer architecture classes. The PYNQ cluster is part of the NSF-funded novel architecture testbed, the Rogues Gallery [34], a center-based testbed that is focused on near-term "post-Moore" computing including nextgeneration HPC, neuromorphic, near-memory, and reversible computing amongst other topics. The PIs of this Center for Research into Novel Computing Hierarchies (CRNCH) work closely with Georgia Tech's high-performance computing organization, the Partnership for an Advanced Computing Environment (PACE).…”

Section: Cluster Overview -Ice and Crnch Rgmentioning

confidence: 99%

Enhancing HPC Education and Workflows with Novel Computing Architectures

Young¹,

Jezghani²,

Valdez³

et al. 2022

JOCSE

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Recent HPC education efforts have focused on maximizing the usage of traditional-and cloud-based computing infrastructures that primarily support CPU or GPU hardware. However, recent innovations in CPU architectures from Arm and RISC-V and the acquisition of Field-Programmable Gate Array (FPGA) companies by vendors like Intel and AMD mean that traditional HPC clusters are rapidly becoming more heterogeneous.This work investigates one such example deployed at Georgia Tech -a joint workflow for processor design and reconfigurable computing courses supported by both the HPC-focused Partnership for an Advanced Computing Environment (PACE) and GT's novel architecture center, CRNCH. This collaborative workflow of HPC nodes and 40 remotely accessible Pynq devices supported over 100 students in Spring 2022, and its deployment provides key lessons on sticking points and opportunities for combined HPC and novel architecture workflows.

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Experimental Insights from the Rogues Gallery

Cited by 12 publications

References 33 publications

Multifaceted Approaches for Introducing a Hardware-Thread Migratory Architecture

Multifaceted Approaches for Introducing a Hardware-Thread Migratory Architecture

A Methodology for Evaluating the Energy Efficiency of Post-Moore Architectures

Enhancing HPC Education and Workflows with Novel Computing Architectures

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