Experimental investigation of the rapid thermal process slip window

Abstract

Throughout the history of rapid thermal processing the generation and subsequent elimination of crystalline slip has been an ongoing battle. The combination of high temperatures, temperature gradients, and strain rates typically present in RTPIRTA systems often result in the deformation of the silicon substrate which in turn, leads to problems with lithographic overlay. In recent years, the issue has become more troublesome as technologies continue to scale. A number of events have been documented at IBM where qualified, healthy machines have impacted process yield via the permanent (albeit subtle) deformation of product wafers. Even though a strong correlation between RTP, stress/slip, and overlay failure has been established in the past this work was an attempt to investigate the more subtle nature of recent events in an empirical and systematic fashion. To that end a multi-faceted study was conducted with three specific objectives; (I) to elucidate the relationship between process conditions and overlay failure, (2) to develop a robust automated measurement for stress/slip detection, and (3) to use those techniques and results as a basis from which to better define process windows and manufacturing control strategies. Results from this investigation indicated a critical dependence on pyrometer offset deltas at the wafer edge with values as small as +2C found to produce unacceptable levels of stress. In all cases, the temperature offset window was found to be -IOC wide with the exact location of the slip free conditions dependent on the particulars of the processes and the process chamber.