Experiments and analysis to characterize logic state retention limitations in 28nm process node

Dasnurkar, Sachin Dileep; Datta, Animesh; Abu-Rahma, Mohamed H.; Nguyen, Hoan; Villafana, M.; Rasouli, Hamed; Tamjidi, S.; Cai, Ming; Sengupta, Shubhalakshmi; Chidambaram, P.R.; Thirumala, R.; Kulkarni, N.; Seeram, P.; Bhadri, Prasad; Patel, P.; Yoon, Sei Seung; Terzioglu, E.

doi:10.1109/vts.2013.6548879

Cited by 2 publications

(1 citation statement)

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“…Power-gating eliminates the static leakage but with no intention to retain the system state. As mobile devices are required to support many features and functions, resulting in a wide range of multitasking, a minimum delay for the state restoration of all active tasks is critical for user satisfaction [7]. Besides the additional delay, saving and restoring the system state presents additional dynamic power overhead that may not be acceptable for certain common applications.…”

Section: Introductionmentioning

confidence: 99%

A New Physical Design Flow for a Selective State Retention Based Approach

Rabinowicz

Greenberg

2021

JLPEA

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This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools.

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Section: Introductionmentioning

confidence: 99%