EXPERT: Effective and flexible error protection by redundant multithreading

So, Hwisoo; Didehban, Moslem; Ko, Yohan; Shrivastava, Aviral; Lee, Kyoungwoo

doi:10.23919/date.2018.8342065

Cited by 24 publications

(25 citation statements)

References 16 publications

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“…Instead, those variations are caused by the initial core state (e.g. branch predictor state), or changes in instruction cache behavior due to changes in the memory alignment of the binaries with and No [12], [28], [31], [32], [4], [25], [33], [34] GPU Partially [2] No [7], [19], [38], [39] without thread redundancy. In the case of FAC benchmark, since it is a small benchmark (around 700 instructions only), these tiny effects have a visible impact in relative terms (e.g.…”

Section: B Execution Time Overheadmentioning

confidence: 99%

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping

Bas

Alcaide

Lorenzo

et al. 2021

2021 IEEE 27th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Safety-related systems, such as those in automotive, avionics and space, impose the existence of appropriate safety measures to meet the safety requirements of the system. In the case of the highest integrity level functionalities (e.g. ASIL-D in automotive), diverse redundancy must be deployed to avoid unreasonable risk of a single fault leading the system to a failure (e.g. using lockstepped cores). However, existing lockstep solutions are either (1) highly intrusive and inflexible coupling two cores with hardware means, or (2) costly in terms of execution time and monitoring if a software monitor thread checks that cores running redundantly preserve sufficient staggering.This paper presents SafeDE, a Diversity Enforcement hardware module providing light-lockstep support by means of a non-intrusive and flexible hardware module that preserves staggering across cores running redundant threads, thus bringing time diversity. SafeDE reconciles the lightness and flexibility of software-only solutions, even allowing using the cores without any lockstepping, as well as the tighter staggering of hardware-only solutions that allow using staggering values of few cycles, instead of hundreds of microseconds, as for software-only solutions. Our integration of SafeDE in a RISC-V FPGA-based space multicore from Cobham Gaisler shows that staggering is effectively preserved, and SafeDE overheads are negligible in terms of area and performance due to staggering. 1 Available as an open-source component in https://bsccaos.github.io [6].

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Section: B Execution Time Overheadmentioning

confidence: 99%

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping

Bas

Alcaide

Lorenzo

et al. 2021

2021 IEEE 27th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…COMET [17] uses a lock-free queue designed by protected memory regions. EXPERT [42] eliminates the vulnerable input replication and output comparison of SOR. However, such technologies can only achieve error detection.…”

Section: B Redundant Muti-threading and Motivationmentioning

confidence: 99%

“…Synchronization between threads is necessary to ensure that RMT runs correctly. The main thread's waiting for the redundant threads occupies a significant role in the extra time overhead [20] [42]. FISHER requires two synchronization operations of the main thread waiting for the redundant threads in each error detection point.…”

Section: Fernando Implementationmentioning

confidence: 99%

FERNANDO: A Software Transient Fault Tolerance Approach for Embedded Systems Based on Redundant Multi-Threading

Guo

2021

IEEE Access

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As semiconductor technology scales, modern microprocessors are more vulnerable to transient faults. Software-level fault tolerance schemes are promising because they can improve reliability effectively without extra hardware. Redundant Multi-threading (RMT) uses off-the-shelf cores as redundancy to achieve error resilience. Latest software RMT fault-tolerance models do not effectively cope with transient faults occurring on multiple components during the application execution, resulting in a large number of silent data corruptions (SDC). To address this challenge, we propose FERNANDO, a software-level RMT runtime fault tolerance scheme which provides enhanced error detection and comprehensive error recovery by Triple-Modular Redundancy (TMR). On an ARM Cortex-A57 like simulated microprocessor, we performed probability model transient fault injection experiments in different components of all cores. The results demonstrate that, compared to the state-of-the-art technique, FERNANDO can reduce the SDC rate by about 86.67 percent and optimize the execution time overhead by about 19.64 percent.

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“…No [18], [19], [20], [21], [22], [23], [24], [25] GPU Partially [3] No [26], [27], [28], [29] [30] implement DCLS, whereas some Arm Cortex-R5 designs implement Triple-Core Lockstep [5], but fail to provide enough performance for AD systems [31]. Some improvements shorten time-to-detection for errors [32] or enhance recovery processes [33], but do not improve performance.…”

Section: Our Approachmentioning

confidence: 99%

“…However, those solutions require hardware support for thread synchronization, and differently to DCLS, do not guarantee diversity. SW-only solutions also exist for CPUs, introducing redundancy at compiler levels [21], [22], building on transactional memory [18] or creating a monitoring process to check for errors [19], [24], among other solutions [25]. However, none of them guarantees staggering execution for redundant threads/processes, so CCFs may cause the same error in both threads/processes, which may lead to a failure.…”

Section: Our Approachmentioning

confidence: 99%

Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms

Alcaide

Kosmidis

Hernández

et al. 2020

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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High-Performance Computing (HPC) platforms become a must in automotive systems to enable autonomous driving. However, automotive platforms must avoid Common Cause Failures (CCFs), as indicated by the ISO26262 automotive safety standard. CCFs can be avoided enforcing diverse redundancy. Unfortunately, HPC platforms fail to provide such support. This paper proposes a flexible and efficient software-based scheme to implement diverse redundancy on HPC platforms. A software implementation on a Commercial Off-The-Shelf ARM multicore proves the effectiveness of this scheme to guarantee diverse redundancy with negligible performance degradation. Our solution is the first step towards an automotive-compliant HPC platform.

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EXPERT: Effective and flexible error protection by redundant multithreading

Cited by 24 publications

References 16 publications

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping

FERNANDO: A Software Transient Fault Tolerance Approach for Embedded Systems Based on Redundant Multi-Threading

Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms

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