Exploiting Dark Cores for Performance Optimization via Patterning for Many-core Chips in the Dark Silicon Era

Wang, Xiaohang; Singh, Amit Kumar; Wen, Shengyan

doi:10.1109/nocs.2018.8512169

Cited by 11 publications

(10 citation statements)

References 19 publications

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“…Although recent proposed DTMs [10,13] employ analytical thermal models to predict per-core temperature by profiling the applications at design time, these DTMs prevent thermal monitoring due to the high computational costs and the data-dependency algorithms. Another alternative to avoid thermal monitoring is patterning the many-core to map applications [9]. Patterning mapping may lead to either resources underutilization (excessive number of dark cores) or communication performance degradation to meet power and temperature requirements.…”

Section: Related Workmentioning

confidence: 99%

“…The first one is to present the Chronos platform, which abstractly models an NoC-based many-core with an instruction-cycle accuracy by using power characterization at the RTL level. The second goal is to apply a DTM heuristic for large-scale systems (64 cores) and perform a comparison of the proposed heuristics with static mapping techniques, such as patterning (dark silicon technique [9,10]) and spiral (performance-driven heuristic [11]).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling

Silva

Weber

Martins

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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For years, transistor size reduction led to a linear decrease in power dissipation. This is the Dennard scaling law, which ended in 2000's technology nodes because the supply voltage no longer scales. The consequence is the increase of the power density in integrated circuits, leading to high temperatures, accelerating aging effects. Dynamic thermal management (DTM) is a technique adopted at runtime to act in the system using the components' current temperature to minimize hotspots and peak temperatures. This paper aims to present a DTM for NoC-based many-cores, using an abstract model, to estimate the temperature at the processing element level and task migration as the main actuation mechanism. Results show up to 12% of temperature reduction and almost 10 o C of peak temperature reduction, highlighting the approach's effectiveness, compared to the pattering and spiral mappings.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling

Silva

Weber

Martins

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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show abstract

“…Some studies used dark cores to migrate the tasks. Studies in [26]- [29] used a virtual task migration to pattern the active and dark cores for optimizing the communication and computation performance of dark silicon many-core systems. This technique moves the location of dark cores and not the actual tasks.…”

Section: Related Workmentioning

confidence: 99%

PEW: Prediction-Based Early Dark Cores Wake-up Using Online Ridge Regression for Many-Core Systems

Mohammed¹,

Paraman

Rahman

et al. 2021

IEEE Access

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Future many-core systems need to address the dark silicon problem, where some cores would be turned off to control the chip's thermal and power density, which effectively limits the performance gain from having a large number of processing cores. Task migration technique has been previously proposed to improve many-core system performance by moving tasks between active and dark cores. As task migration imposes system performance overhead due to the large wake-up latency of the dark cores, this paper proposes a prediction-based early wake-up (PEW) to reduce the dark cores' wake-up latency during task migration. A window-based online ridge regression (RR) is used as the prediction model. The prediction model uses the past window's thermal, power, and core status (i.e., active or dark) to predict the future core temperatures at run-time. If task migration is predicted in the next control period, the proposed PEW puts the dark cores in a power state with low wake-up latency. Thus, the proposed PEW reduces the time for the dark cores to start executing the tasks. The comparison results show that our proposed PEW reduces the completion time by up to 7.9% and 4.1% compared to non-early wake-up (NoEW) and a fixed threshold wake-up (FEW), respectively. It also shows that the proposed PEW increases the MIPS/Watt by up to 5.5% and 2.3% over NoEW and FEW, respectively. These results show that the proposed PEW improves the many-core system's overall performance in terms of reducing dark cores' wake-up latency and increasing the number of executed instructions per Watt.INDEX TERMS Dark silicon, many-core systems, task migration, dynamic voltage frequency scaling (DVFS), ridge regression, early wake-up, dark core wake-up latency.

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“…However, the above mapping approaches still do not exploit dark cores for better performance [8]. Although an early study in [9] presents a dark-core-aware migration algorithm to produce better computation performance, it does not address the changing computation demands of applications.…”

Section: B Dynamic Mapping With Task Migrationmentioning

confidence: 99%

“…In anticipation that "cold" dark cores can be used for heat dissipation purposes, when an application is mapped to run on active cores, a few dark cores can also be allocated to the same application. There have been a number of studies on mapping applications to both active and dark cores [4]- [9]. They basically allocate dark cores to applications in the way that the active cores are allowed to operate at higher frequency levels, and thus, achieve higher performance at a cost of higher power consumption.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Allocation/Reallocation of Dark Cores in Many-Core Systems for Improved System Performance

et al. 2020

Self Cite

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A significant number of processing cores in any many-core systems nowadays and likely in the future have to be switched off or forced to be idle to become dark cores, in light of ever increasing power density and chip temperature. Although these dark cores cannot make direct contributions to the chip's throughput, they can still be allocated to applications currently running in the system for the sole purpose of heat dissipation enabled by the temperature gradient between the active and dark cores. However, allocating dark cores to applications tends to add extra waiting time to applications yet to be launched, which in return can have adverse implications on the overall system performance. Another big issue related to dark core allocation stems from the fact that application characteristics are prone to undergo rapid changes at runtime, making a fixed dark core allocation scheme less desirable. In this paper, a runtime dark core allocation and dynamic adjustment scheme is thus proposed. Built upon a dynamic programming network (DPN) framework, the proposed scheme attempts to optimize the performance of currently running applications and simultaneously reduce waiting times of incoming applications by taking into account both thermal issues and geometric shapes of regions formed by the active/dark cores. The experimental results show that the proposed approach achieves an average of 61% higher throughput than the two state-of-the-art thermal-aware runtime task mapping approaches, making it the runtime resource management of choice in many-core systems. INDEX TERMS Dark core, many-core, dynamic resource allocation, throughput optimization.

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Exploiting Dark Cores for Performance Optimization via Patterning for Many-core Chips in the Dark Silicon Era

Cited by 11 publications

References 19 publications

Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling

Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling

PEW: Prediction-Based Early Dark Cores Wake-up Using Online Ridge Regression for Many-Core Systems

Dynamic Allocation/Reallocation of Dark Cores in Many-Core Systems for Improved System Performance

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