Exploiting dynamic transaction queue size in scalable memory systems

Abstract

In order to increase parallelism via memory width in scalable memory systems, a straightforward approach is to employ larger number of memory controllers (MCs). Nevertheless, a number of researches have pointed out that, even executing bandwidth-bound applications in systems with larger number of MCs, the number of transaction queue entries is under-utilized -namely as shallower transaction queues, which provides an opportunity to power saving. In order to address this challenge, we propose the use of transaction queues with dynamic size that employs the most adequate size, taking into consideration the number of entries utilized while presenting adequate levels of bandwidth and minimizing power. Experimental results show that, while saving up to 75% number of entries, the introduction of dynamic transaction queue mechanism can present savings up to 75% of bandwidth and 20% of rank energy-per-bit reduction compared to systems with 1-2ntries. With such promising results, it can be aimed and incorporated in modelling methodologies directed to the design and evaluation of new generation embedded systems.

Research on global register allocation for code containing array‐unit dual‐usage register names

“…Thus, people are facing the need for more efficient systems. It has been found that this can be mitigated by optimizing the number of memory controllers or the on‐chip bandwidth configuration 18–20 . In order to enhance the data processing ability of the chip at a deeper level, more advanced vector architecture processors have been proposed 21,22 .…”

“…It has been found that this can be mitigated by optimizing the number of memory controllers or the on-chip bandwidth configuration. [18][19][20] In order to enhance the data processing ability of the chip at a deeper level, more advanced vector architecture processors have been proposed. 21,22 Vector DSPs for high-speed data processing is one of the typical processors.…”