Exploiting HBM on FPGAs for Data Processing

Shi, Runbin; Kara, Kaan; Hagleitner, Christoph; Diamantopoulos, Dionysios; Syrivelis, Dimitris; Alonso, Gustavo

doi:10.1145/3491238

Cited by 7 publications

(5 citation statements)

References 45 publications

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“…The selection and screening process Latency: Latency is a prominent concern impacting the responsiveness of user-centric protocols. Latency in TCP/IP networks, often referred to as the time it takes for a data packet to travel from its source to its destination, is a critical performance metric that affects the user experience and the efficiency of networked applications [121], [122]. Factors contributing to latency include the physical distance between communicating nodes, the number of hops (intermediate devices like routers and switches) data packets must traverse, the quality and capacity of the network connections, and the congestion levels on the network.…”

Section: Figurementioning

confidence: 99%

Performance, privacy, and security issues of TCP/IP at the application layer: A comprehensive survey

Timothy Murkomen

2024

GSC Adv. Res. Rev.

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TCP/IP is the backbone of modern network communication, connecting devices across the world. TCP/IP at its core is a suite of protocols that enables the transmission of data between computers, facilitating the foundation of the interconnected global network. At the Application Layer of TCP/IP is where the interaction between software applications and the network occurs. The user-centric protocols such as HTTP, SMTP, FTP, POP3, IMAP and DNS facilitate various tasks at this layer such as web browsing, email communication, and file transfer. This comprehensive survey conducted an exploration of the performance, security and privacy issues at the application layer of the TCP/IP. It initiated by providing a background of TCP/IP model, it’s architecture and the core characteristics, with major focus on the application layer. This paper aimed to discuss the state-of-the-art of performance, privacy and security concerns in TCP/IP application layer. It also proposed future research areas to equip researchers, practitioners, policy makers and the decision makers with tangible knowledge, offering guidance in navigating the performance, privacy and security concerns in TCP/IP Application Layer. It aimed to discuss the current performance, privacy and security research gaps at the Application Layer of the TCP/IP Model. The findings of this research sheds light on the performance, privacy and security issues while suggesting the countermeasures to strengthen and optimize the overall performance, security and privacy of TCP/IP model at the application layer. The paper finally suggests future directions and research areas at the TCP/IP application layer.

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Section: Figurementioning

confidence: 99%

Performance, privacy, and security issues of TCP/IP at the application layer: A comprehensive survey

Timothy Murkomen

2024

GSC Adv. Res. Rev.

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“…Compared to ASICs, FPGAs provide abundant internal resources, a shorter design cycle, high flexibility, and lower costs [21,22]. These advantages have led to the widespread utilization of FPGA in various research fields, including multimedia database query processing, autonomous driving, embedded systems, artificial intelligence, communication, and electrical engineering [23][24][25][26][27][28].…”

Section: State Of the Artmentioning

confidence: 99%

Development and Implementation of an FPGA-Embedded Multimedia Remote Monitoring System for Information Technology Server Room Management

Zhu,

Hou

2024

International Journal of Digital Multimedia Broadcasting

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Conventional data acquisition systems face challenges in achieving high acquisition speeds and rapid storage of large data volumes using microcontrollers. In contrast, field-programmable gate arrays (FPGAs) offer numerous advantages, including high clock frequencies, minimal internal delays, fast operational speeds, abundant internal RAM resources, and simplified control of complex peripheral circuits. This study presents the design of an FPGA-based multimedia remote monitoring system for information technology server rooms. The proposed system utilizes an FPGA as the primary controller and incorporates environmental sensors, electrical energy sensors, carbon monoxide sensors, smoke sensors, and A/D converter modules to monitor multiple locations within the server room. Simultaneously, the FPGA transmits the collected data from each monitoring point via a serial port to an LCD serial screen for display. An alarm is triggered if any environmental anomalies are detected, indicating abnormal statuses. Additionally, the system employs the fast Fourier transform algorithm and butterfly operations to derive voltage and current AC quantities, while utilizing relative temperature differences to identify equipment faults within the server room. The system is evaluated in terms of functionality, user-friendliness, and reliability. Experimental results demonstrate that all performance measures align with expectations, fulfilling the initial design objectives and highlighting the potential applicability and relevance of FPGA technology in the monitoring field. In addition, a comparison between FPGA and traditional microcontroller systems is performed, showcasing the superior processing speed and performance of the FPGA-based system. This comparative analysis further validates the advantages of using FPGA technology in high-speed data acquisition and monitoring applications.

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“…The Xilinx Alveo U50 FPGAs [33] have been bonded with HBM stacks within the same chip package, enabling ultra-wide memory interconnections [34]. HBM provides the bandwidth, energy efficiency, and memory architecture flexibility to adapt to various applications [35].…”

Section: High Bandwidth Memorymentioning

confidence: 99%

A High-Performance Non-Indexed Text Search System

Kieu-Do-Nguyen,

Dang,

The Binh

et al. 2024

Electronics

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Full-text search has a wide range of applications, including tracking systems, computer vision, and natural language processing. Standard methods usually implement a two-phase procedure: indexing and retrieving, with the retrieval performance entirely dependent on the index efficiency. In most cases, the more powerful the index algorithm, the more memory and processing time are required. The amount of time and memory required to index a collection of documents is proportional to its overall size. In this paper, we propose a full-text search hardware implementation without the indexing phase, thus removing the time and memory requirements for indexing. Additionally, we propose an efficient design to leverage the parallel architecture of High Bandwidth Memory (HBM). To our knowledge, few (if not zero) researchers have integrated their full-text search system with an effective data access control on HBM. The functionality of the proposed system is verified on the Xilinx Alveo U50 Field-Programmable Gate Array (FPGA). The experimental results show that our system achieved a throughput of 8 Gigabytes per second, about 6697× speed-up compared to other software-based approaches.

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Exploiting HBM on FPGAs for Data Processing

Cited by 7 publications

References 45 publications

Performance, privacy, and security issues of TCP/IP at the application layer: A comprehensive survey

Performance, privacy, and security issues of TCP/IP at the application layer: A comprehensive survey

Development and Implementation of an FPGA-Embedded Multimedia Remote Monitoring System for Information Technology Server Room Management

A High-Performance Non-Indexed Text Search System

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