Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile Platforms

On-Chip Dynamic Resource Management

“…In this perspective, the works by Baldassari et al (2017); Mück et al (2017) define two similar reliability-aware run-time resource management controllers for the big.LITTLE multi-core architecture. As for many previous works on different architectures, the controller exploits a feedback loop to sense power consumption, temperature and workload performance; after that, reliability is computed based on temperature sensing by means of a stochastic model (EM is considered by Baldassari et al (2017) while NBTI and HCI by Mück et al (2017)). Regarding performance measures, hardware performance counters are used by Mück et al (2017), while application-level throughput measures are performed by Baldassari et al (2017).…”

“…As for many previous works on different architectures, the controller exploits a feedback loop to sense power consumption, temperature and workload performance; after that, reliability is computed based on temperature sensing by means of a stochastic model (EM is considered by Baldassari et al (2017) while NBTI and HCI by Mück et al (2017)). Regarding performance measures, hardware performance counters are used by Mück et al (2017), while application-level throughput measures are performed by Baldassari et al (2017). Then, both the two approaches feature a decision policy based on predictive models for performance, power consumption and aging, aimed at selecting for each application to be executed the most suitable unit capable of satisfying reliability constraint and performance requirements and minimizing the power consumption.…”

Simulating Wear-out Effects of Asymmetric Multicores at the Architecture Level

“…Even Intel's multicore processors using Turboboost technology could be also considered as dynamically asymmetric architectures. Such asymmetric designs, however, can affect in a non-uniform manner reliability-related parameters, such as the temperature, voltage and frequency, and unavoidably manifest into variable lifetimes [7][8] [25] [33], unlike the symmetric designs. As a result, some components might age faster, leading to earlier performance degradation with eventual device breakdown.…”

“…To guarantee correct operation throughout the lifetime of a processor, computer architects mainly provide worst-case timing guard-bands and runtime wear-out mitigation techniques. Among them, the most common state-of-the-art methods are wear-out monitoring through sensors [1] [4] [23], aging-aware scheduling [25] [30] [35], dynamic voltage and frequency scaling (DVFS) [9] [24], and spare structures [19] [34] to replace malfunctioning components and mitigate aging [18]. In addition, previous reliability studies [5] [13] [26] introduced wear-out estimation methodologies and assessed the vulnerability of symmetric multicore hardware designs on device degradation phenomena.…”